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A blank, flickering, or bar-filled image usually means one of five things is wrong: the source mode is unsupported or misidentified, the DE-9 input is wired incorrectly, the sync signals never reach the RP2350, the pixel sampling phase is wrong, or the firmware is using the wrong board pin map. Troubleshoot in that order. The pico-ttl2dvi design separates source detection, TTL capture, and DVI output, so a serial status check and a standalone output test can tell you which section has failed.
This guide applies directly to the documented pico-ttl2dvi project and to similar RP2350 designs that use PIO and DMA to capture retro computer video. “TTL video” is not one universal timing format: MDA/Hercules, CGA, Commodore 128 VDC, and EGA use different data lines, line rates, and dot clocks.
Start by identifying the source signal
Write down the graphics card or computer, its video mode, connector pinout, horizontal and vertical sync polarity or behavior, and expected dot clock. Do this before changing firmware. The converter’s source profiles are not interchangeable, and a wrong profile can make a correctly wired signal look absent.
| Source family | Video data presented to the input | Documented dot-clock configuration | Important qualification |
|---|---|---|---|
| MDA/Hercules | VIDEO and INTENSITY (two data lines) | 16.000 MHz | Project configuration value; individual cards can differ. |
| CGA | RGBI | Approximately 14.323 MHz | Use the source profile that matches the actual mode. |
| Commodore 128 VDC | Project-specific VDC data and sync lines | 16.000 MHz | This is a documented source family, not a guarantee for every VDC implementation. |
| EGA, 200-line modes | RGBI-style color data | 17.750 MHz or 14.161 MHz, depending on line mode | The secondary color-line behavior changes between 200- and 350-line operation. |
| EGA, 350-line modes | Six color lines | Mode-dependent value above | Do not assume the 200-line wiring or timing applies. |
These values come from the project’s source profiles. They are not universal specifications for every revision of a graphics card. If you cannot establish the mode, use the serial measurement and detection functions rather than guessing from the connector.
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Why the mode matters
The RP2350 must sample data at the source’s pixel rate while recognizing its sync timing. MDA/Hercules’ two data lines, CGA’s RGBI arrangement, and EGA’s six-line 350-row arrangement place different electrical and timing requirements on the same general connector concept. A monitor that accepts the resulting DVI signal does not prove that the RP2350 is sampling the TTL source correctly.
Record whether the source is in a text or graphics mode and whether it changes modes during boot. A profile that works at one timing can fail immediately after a mode switch. For EGA in particular, verify both the row mode and the color-line arrangement before treating a missing color channel as a sampling fault.
Inspect the physical input before tuning firmware
For the documented direct-input circuit, DE-9 video and sync lines pass through 330-ohm series resistors to RP2350 GPIO 20–27. DE-9 pin 1 is the common ground. Follow the project’s complete pin table for the selected source; connector appearance is not a reliable way to infer signal order.
- Check every data line for continuity from the DE-9 pin, through its 330-ohm resistor, to the assigned GPIO.
- Verify that HSYNC and VSYNC are not swapped.
- Confirm that the source, input circuit, and RP2350 share ground through DE-9 pin 1.
- Look for cold solder joints, a partially inserted connector, damaged resistors, or a cable wired for a different video standard.
- Keep the documented power sequence: power the Pico before the PC, and power the PC down before removing power from the Pico.
The direct circuit relies on the RP2350 pad clamps and resistor current limiting. It is not permission to connect an arbitrary video source directly to a GPIO or to omit the series resistors. A continuity check with power removed is useful, but it cannot prove that a line has the correct logic level under load; inspect the actual circuit and its resistor values as well.
Buffered input: 74HCT541
The documented 74HCT541 arrangement provides a 5 V buffer. Its outputs use 330-ohm resistors before the RP2350 inputs. Ground the device’s /OE pins, power it as specified by the project, and connect the card, buffer, and Pico grounds together. The project calls for HCT rather than plain HC because the input-threshold behavior is appropriate for the TTL levels involved.
Check both output-enable pins individually. A single enable left high or floating can disconnect part of the bus and produce a picture that appears to have missing colors or unstable sync. Confirm local decoupling and that the buffer supply is present before probing the RP2350 side.
Buffered input: 74LVC245A
The alternative 74LVC245A circuit is a distinct design, not a drop-in combination of parts from the HCT541 schematic. It is powered at 3.3 V, has 5.5 V-tolerant inputs according to the project documentation, and must be configured for A-to-B operation with DIR high and /OE low. Follow the project’s resistor placement and supply connections exactly.
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Do not substitute a generic level-shifter module and assume it has the same direction control, edge rate, voltage tolerance, or termination. A floating enable pin can leave all captured lines effectively disconnected, while mixing the two circuits can put the wrong voltage or resistor arrangement on the RP2350 pins. The 74HCT541 and 74LVC245A options also differ in supply voltage and control pins, so label the design you actually built before comparing symptoms with someone else’s wiring.
Check whether sync reaches the firmware
Connect to the project’s USB CDC serial console at 115200 baud. Use the available commands as diagnostic stages:
- Run
statusto see the current operating state and whether a source has been selected. - Run
stateto inspect the capture state reported by the firmware. - Run
measureto obtain measured timing, including sync-related values and dot-clock information. - Run
detectto let the source-recognition logic compare the measured line rate and dot clock with known profiles. - Use
sourceto select or confirm the intended source profile before attempting capture.
The sync logic measures HSYNC period and pulse width, checks rates against known ranges, and uses line rate plus measured dot clock to identify a supported source. A stable result here is more useful than a DVI monitor’s “no signal” message, because it proves that the capture side is seeing timing information.
If no stable sync is reported
Stop at this point and return to the source and wiring. Recheck the card’s output mode, the DE-9 pinout, common ground, HSYNC/VSYNC routing, buffer power, and buffer enable pins. Inspect the source while it is known to be running a supported mode. Pixel-phase tuning cannot recover a signal for which the firmware sees no repeatable sync.
Take several readings rather than relying on one transient result. A value that changes substantially between commands suggests an intermittent connection, marginal edge, or source that is changing modes. If sync appears only when the cable is moved, fix the connector or grounding problem before storing any timing values.
If sync is present but detection is wrong
Compare the measured line rate and dot clock with the expected mode. A card oscillator that differs from the default profile can fall outside an assumed range or select a neighboring profile. Confirm that the source’s 200-line versus 350-line EGA wiring is correct, then select the matching source explicitly and measure again.
Do not “solve” a detection mismatch by selecting an unrelated profile merely because it produces an image. The wrong profile can map data bits incorrectly, create false colors, or make a marginal clock appear to work only until the source changes mode.
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Understand what PIO and DMA can—and cannot—fix
The RP2350 contains three PIO blocks, each with four state machines, and a DMA interface capable of sustained throughput of up to one word per clock from system DMA, according to the official RP2350 datasheet. PIO provides deterministic programmable I/O; DMA moves captured words without asking the CPU to service every pixel. The converter captures around a VSYNC-bounded frame and samples around HSYNC edges.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsThose capabilities make a timing-sensitive video pipeline practical, but they do not automatically make every TTL format compatible. PIO cannot correct a swapped connector, a missing ground, an unsupported dot clock, or a buffer held in disable. Treat “the RP2350 is powerful enough” and “this source profile is configured correctly” as separate questions. A successful DVI test also does not prove that the capture PIO is receiving valid source data; each path needs its own test.
Tune a picture that is recognizable but unstable
Shimmering text or evenly spaced vertical bars generally means the source is being recognized but the sampling point is not centered reliably on each pixel. The project specifically describes this symptom when a source card’s crystal differs from the default timing.
- Display text or a high-contrast test pattern from the source. A stable, repeated pattern makes shimmer and bars easier to judge.
- Run the firmware’s
tunecommand, or open the menu and choose Sampling → Auto tune. - Let the routine measure the dot clock and search the documented range around the current clock.
- Inspect the reported result and apply it. Save the setting only after the image remains stable through a mode change or reset.
- Use
measureand capture/status functions if the search finds no convincing result.
Auto tune chooses a clock and phase; it does not adjust bp, the left edge. A picture can therefore be stable but horizontally displaced or cropped. Treat framing as a separate adjustment after sampling is reliable.
When auto tune still shimmers
- Verify that the selected profile matches the measured source; tuning the wrong dot-clock family can produce a locally plausible but unstable result.
- Check whether the source clock has a non-integral relationship to the RP2350 system clock. The project warns that such a relationship can leave residual shimmer even after tuning.
- Repeat the test with a clean text screen rather than a moving or scrolling display.
- Recheck the input resistor path and buffer supply. A marginal edge can look like a phase problem.
- Measure again after changing modes; do not assume a setting for one card or mode is valid for another.
Change one variable at a time. If you alter the source profile, phase, and framing together, you lose the ability to tell which change helped. Save a known-good setting only after observing a stable image for the mode you intend to use.
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The converter has independent capture and DVI output paths. Its default board target is the Waveshare RP2350-PiZero, where the documented DVI output uses GPIO 32–39. A different RP2350 carrier may route those signals elsewhere. Confirm the board selection in the project configuration before diagnosing the display.
Use the standalone output test
The project includes a standalone dvi_test application. Run it with the TTL source disconnected or otherwise isolated. If the test pattern is not produced, investigate the board target, GPIO 32–39 routing, DVI connector and cable, display input selection, and power. If the standalone output works but captured video does not, return to source compatibility, sync acquisition, and sampling rather than replacing the DVI hardware.
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Check the display input selection explicitly; a monitor left on another input can make a working output look dead. Likewise, test with the same cable and board power arrangement used for the converter, because changing several physical variables at once obscures the fault boundary.
The RP2350 datasheet lists DPI or VGA through a resistor DAC among possible interfaces. That general capability does not define this project’s DVI pin map or capture implementation; those are supplied by the converter’s board configuration and firmware.
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Use a fault-isolation decision path
- Blank display and no serial sync: verify source mode, connector wiring, DE-9 pin 1 ground, resistor continuity, buffer power/enable, and HSYNC/VSYNC routing.
- Serial sync present but no recognized source: measure line rate and dot clock, compare them with the source table, and select the correct profile.
- Recognized source with shimmer or vertical bars: run
tuneor Sampling → Auto tune, then inspect phase and measured clock. - Stable image with incorrect left edge: adjust framing separately; auto tune does not change
bp. - Capture appears valid but the display is blank: run
dvi_test, verify the board target and GPIO 32–39 mapping, then check the cable and monitor input. - Intermittent behavior after rewiring: inspect enable pins, decoupling, shared ground, connector strain, and the documented power-up/down order before changing timing values.
Record the RP2350 silicon stepping
Raspberry Pi’s 29 July 2025 announcement says the A4 stepping fixed Erratum 9, a GPIO-pad leakage issue associated with the original A2 stepping. Record the stepping when comparing boards or investigating a GPIO design that behaves differently between units. The announcement does not establish that Erratum 9 causes TTL-video instability, nor that A4 is required for this converter, so stepping alone is not a diagnosis.
Documented input choices at a glance
| Approach | Electrical arrangement | Advantages | Checks and limitations |
|---|---|---|---|
| Direct input | 330-ohm series resistors from DE-9 signals to GPIO 20–27 | Fewest parts and simplest wiring | Depends on pad clamping and current limiting; strict grounding and power sequencing matter. |
| 74HCT541 buffer | 5 V buffer, 330-ohm resistors on outputs, /OE grounded |
Buffered 5 V TTL path | Use HCT, not an assumed HC equivalent; verify supply, enables, and shared ground. |
| 74LVC245A buffer | 3.3 V supply, documented 5.5 V-tolerant inputs, DIR high and /OE low |
3.3 V alternative with controlled direction | Different topology and resistor placement; do not mix with the 74HCT541 circuit. |
A separate RP2350 VGA example uses a weighted resistor DAC with 470-ohm and 1-kilohm color resistors plus 100-ohm sync resistors and a common ground. That is an output circuit for VGA and is not a substitute for the TTL-input protection or pin map used by pico-ttl2dvi.
Choose the input arrangement based on the documented schematic you can build and verify. The direct option has fewer components but depends on the stated resistor and sequencing precautions. The buffered options add an IC and control-pin checks while providing a defined interface. None is automatically equivalent to an unspecified level-shifter board.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What to write down before asking for help
- RP2350 board model and silicon stepping, plus the firmware version and board target selected at build time.
- Source computer or card, exact video mode, connector and cable type, and expected dot clock.
- Whether the input is direct, 74HCT541-buffered, or 74LVC245A-buffered, including supply voltage and enable-pin states.
- Measured output from
status,state,measure, anddetect. - Whether
dvi_testgenerates a stable output independently of TTL capture. - Whether the symptom is no sync, wrong source detection, shimmer, vertical bars, horizontal framing error, or a DVI-only blank screen.
Include a clear wiring photograph or a pin-by-pin list, especially if the design is hand-wired. State which source profile was selected and whether the symptom changes after a mode switch or power cycle. This information lets a helper separate an electrical fault from a timing or board-configuration fault without guessing.
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Why is my RP2350 TTL-to-DVI display blank?
First check that the source is one of the documented MDA/Hercules, CGA, Commodore 128 VDC, or EGA families and that the matching profile is selected. Then verify DE-9 pin mapping, 330-ohm series resistors, common ground, HSYNC/VSYNC routing, buffer power and enables, and the documented power sequence. Use the 115200-baud serial commands to determine whether sync is reaching the firmware, and run dvi_test to isolate the DVI path.
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Why does the image shimmer or show evenly spaced vertical bars?
This is commonly a sampling-clock or phase problem when the source is recognized, particularly if the source card’s crystal differs from the default timing. Display a stable text pattern, run tune or Sampling → Auto tune, apply the measured result, and save it only after it remains stable. Check the selected profile and input signal quality as well; a non-integral relationship between source and system clocks can leave residual shimmer.
Is the RP2350 detecting HSYNC and VSYNC?
Use status and state for operating information, measure for sync period, pulse width, and dot-clock data, and detect for comparison with known source profiles. If readings are absent or unstable, troubleshoot the source mode, DE-9 wiring, shared ground, sync routing, and buffer controls before attempting phase tuning.
Does my board use the pin mapping expected by this firmware?
The documented default is the Waveshare RP2350-PiZero, with DVI output on GPIO 32–39 and TTL input lines on GPIO 20–27 through the documented circuits. Another RP2350 carrier may route these signals differently. Confirm the board target and configuration rather than assuming physical pin numbers match.
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Should I use direct resistors, a 74HCT541, or a 74LVC245A?
The direct design is the simplest documented path and uses 330-ohm series resistors, but it relies on pad clamping, current limiting, grounding, and power sequencing. The 74HCT541 is a 5 V buffered design with 330-ohm output resistors and grounded /OE pins. The 74LVC245A is a separate 3.3 V design with 5.5 V-tolerant inputs, DIR high, and /OE low. Follow one complete schematic and do not combine parts or wiring between them.
Can auto-tune fix a picture that is shifted or cropped?
No. The documented tuning routine chooses dot-clock and sampling phase but does not adjust bp, the left edge. Tune for a stable picture first, then handle horizontal framing separately.
Does an A4 RP2350 stepping solve TTL-video instability?
Not necessarily. Raspberry Pi’s 29 July 2025 announcement says A4 fixed Erratum 9, a GPIO-pad leakage issue associated with original A2 silicon, but it does not establish that the erratum causes this video fault or that A4 is required. Record the stepping when comparing boards, then continue with source, wiring, sync, timing, and output isolation.
What if dvi_test works but captured video does not?
The DVI output path is probably functioning, so return to source compatibility, input wiring, sync acquisition, profile selection, and sampling phase. A successful standalone output test cannot validate the TTL connector or capture PIO.
The Bottom Line
Diagnose the chain in order: identify the exact source mode, verify the DE-9 wiring and one complete input circuit, confirm stable HSYNC/VSYNC and dot-clock measurements over USB serial, tune sampling only after detection succeeds, and isolate DVI output with dvi_test. Keep the board-specific GPIO map and silicon stepping in your records, but do not treat either as a substitute for electrical and timing checks.
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