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To test a switched-capacitor filter IC, control and measure both the analog input and the clock: the clock helps set the filter’s cutoff or center frequency. Start with the exact part’s data sheet, wire one documented configuration, verify safe operation, then sweep a low-level sine wave while recording the clock, input and output, supplies, and load. The pinout, supply rails, clock ratio, response definition, and limits are device-specific; there is no universal bench hookup.
What the test must establish
A useful bench test answers two different questions. First, does the IC behave as expected in the chosen configuration? Second, does its measured response track the relationship between the clock and the filter frequency stated in the data sheet? A frequency sweep without a measured clock can answer the first question incompletely and the second not reliably.
Switched-capacitor filters use clocked internal circuitry to emulate frequency-dependent behavior. Changing the clock can therefore move the response, but the exact ratio and response landmark depend on the IC and its configuration. A measured cutoff, center frequency, or notch is meaningful only when you know which output and definition apply.
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The procedure below uses the MF10-N as a worked example where its documentation supports a specific point. It is a dual universal filter, not a template for wiring other parts. The TLC04 and TLC14 provide useful contrast because their published clock-to-cutoff ratios differ from one another and from the MF10-N’s configuration-dependent relationship.
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Identify the device and predict its response
Record the configuration before wiring
Write down the complete part number and package, the data-sheet revision, the section and output being tested, and the intended response type. Record the supply and reference arrangement, external resistor values, clock source and mode, expected output load, and the input and output swing limits. For a device with multiple configuration options, note the exact mode selected rather than simply writing “low-pass” or “band-pass.”
Then find the data sheet’s equation for the response landmark you intend to measure. Use the specified clock ratio and any external resistor-dependent terms to calculate an expected cutoff, center frequency, or notch frequency. Check whether the equation refers to the clock frequency at a particular pin or to another frequency definition. Confirm the permitted clock logic levels, duty cycle, and frequency range before connecting a generator.
The MF10-N product information describes a dual universal filter with separate high-pass/notch/all-pass, band-pass, and low-pass outputs. Its center-frequency relationship depends on clock and, in some configurations, external resistor ratios. TI lists ±0.6% clock-to-center-frequency ratio accuracy on the product page; treat that as a product-page feature claim, not as a substitute for checking the full data sheet or as a complete bench uncertainty budget. The page also reports an operating range of 0 to 70 °C and operation up to 30 kHz. Confirm how the applicable limit is defined for your configuration in the current documentation.
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Use a ratio example only where it applies
For a TLC04 configuration using its documented 50:1 clock-to-cutoff relationship, a desired 1 kHz cutoff corresponds to a 50 kHz clock, and a 2 kHz cutoff corresponds to a 100 kHz clock. These are arithmetic examples of that ratio, not universal filter settings or a statement that either setting is suitable for every circuit. TI lists the TLC04’s ±0.8% ratio error and a 0.1 Hz to 30 kHz cutoff range under the stated ±2.5 V supply condition. Check the data sheet for the exact test conditions and limits before choosing a point.
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The TLC14 is a separate device with a 100:1 clock-to-cutoff ratio and ±1% ratio error in the same family information. Those figures do not make the TLC14 interchangeable with the TLC04 or MF10-N: filter function, configuration, supplies, clock requirements, and other limits matter too. The TLC04 product and ordering page showed the TLC04ID out of stock when accessed on 2026-10-13; stock status can change and does not establish the availability of every variant.
Choose instruments and prepare a safe setup
The functional requirements are modest but important: a sine source that covers the test range, a way to generate and measure the IC clock, a suitable supply arrangement, and an oscilloscope or other instrument capable of measuring the response. A frequency-response analyzer or scope-based gain and phase measurement can make a sweep easier to characterize, but the cited data sheets do not prescribe a particular instrument or model.
- Use a supply arrangement that matches the exact IC’s rails, ground, and reference connections.
- Use a clock source with the allowed logic levels, frequency range, and duty cycle for the selected device and mode.
- Use a signal source with sufficient frequency range and controllable amplitude; begin at a small amplitude comfortably inside the documented input and output limits.
- Use probes and connections suitable for observing the clock at the IC pin and the analog input and output. Keep return paths deliberate.
- Know the expected output load. Instrument input impedance, cables, and any external load can affect the observed result, so record what is connected.
These are practical bench requirements inferred from the measurement objective, not a manufacturer-approved universal equipment prescription. In particular, do not assume a scope ground clip can be attached to any node called a reference: check the circuit’s grounding and supply arrangement so the probe does not short a reference to ground.
Wire the documented configuration
With power off, connect the supplies, grounds or references, external resistors, clock mode, and selected output exactly as shown for the chosen IC configuration. Keep the signal and clock wiring organized, and avoid introducing unintended coupling between the clock and analog path. If testing a dual-section part, identify which section is being driven and which output is being observed; a second section may be unused or configured differently.
For the MF10-N, TI says the clock duty cycle should be close to 50%, especially above 200 kHz, to give internal op amps maximum settling time. The data sheet also explains the 50/100/CL mode pin behavior. Verify those requirements for the selected setup rather than applying them indiscriminately to another part.
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Bring up the circuit before the sweep
- Set safe initial conditions. Disable the analog input or set it to a small sine wave. Configure the supply and clock source to the values allowed by the data sheet, but do not energize a circuit with uncertain pin connections.
- Apply power and inspect the rails. Measure the actual supply voltages and confirm the reference arrangement. Check whether supply current is plausible for the device and configuration; use the data sheet rather than an assumed generic current value.
- Verify the clock at the IC. Observe it at the clock pin, not only at the generator output. Record its frequency, logic levels, and duty cycle. Confirm they meet the selected part’s limits.
- Apply a low-level in-band signal. Choose a frequency expected to be within the configured passband and a level well below the documented clipping limits. Check the input and the corresponding output.
- Inspect for abnormal behavior. Look for clipping, unexpected DC offset, oscillation, a missing output, or a response on the wrong output. If the IC offers multiple response outputs, observe the one associated with the selected function.
Do not begin a frequency sweep until the supply, reference, clock, and basic analog path are verified. A wrong mode pin or clock level can produce a plausible-looking waveform that nevertheless represents the wrong configuration.
Measure gain, frequency, and clock tracking
Run a controlled sweep
Hold the clock frequency, supplies, resistor configuration, input amplitude, and output load constant while sweeping the signal generator. Cover the intended operating range, with denser measurement points near the predicted corner, center, or notch. At each point, record the actual input frequency and input and output amplitudes. Also note the measured clock frequency and any phase value needed for the application.
Calculate voltage gain as Vout/Vin. For gain in decibels, calculate 20 log10(Vout/Vin), using consistent amplitude conventions for the input and output measurements. If the waveform is distorted or clipped, an amplitude ratio alone may be misleading; inspect waveform shape as well as magnitude.
Use the data sheet’s response definition when identifying the measured landmark. A low-pass cutoff is commonly specified relative to a passband level, but the exact definition and tolerance must come from the applicable device documentation. A band-pass response has a center frequency and bandwidth or Q; these are separate measurements. Do not label a peak as a cutoff or assume a familiar response convention if the data sheet defines a different one.
Keep a record such as this for every measurement point:
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| Record | What to enter |
|---|---|
| Device and configuration | Full part number, data-sheet revision, section/output, response mode, resistor values, and clock mode |
| Operating conditions | Measured supply rails, reference arrangement, temperature if relevant, and output load |
| Clock | Measured frequency at the IC pin, logic levels, and duty cycle |
| Analog measurement | Input frequency and amplitude, output amplitude, calculated gain, and phase if needed |
| Result quality | Instrument range or resolution, observed distortion or clock-related artifacts, and estimated measurement uncertainty |
Compare the measured landmark with the predicted value and state the resolution or uncertainty of the measurement. A displayed frequency with several decimal places does not demonstrate accuracy at that precision. The clock source’s stability matters because the filter frequency depends on the clock; measure the clock rather than relying only on its generator setting.
Repeat at a second clock setting
To test clock tuning, select a second clock frequency that is within the device’s documented limits. Keep the other conditions unchanged and repeat enough of the sweep to identify the same response landmark. Compare the change in measured filter frequency with the clock relationship or resistor-dependent equation for that configuration. If the predicted shift does not appear, check the clock at the IC pin, clock mode, resistor values, and response definition before concluding that the IC is faulty.
Recognize sampled-data and clock artifacts
Aliasing and unexpected high-frequency response
A switched-capacitor filter is a sampled-data circuit, so input energy near or above half the sampling frequency can fold into a lower frequency. For the MF10-N, TI identifies the sampling frequency as equal to its clock. A high-frequency input component can therefore appear as an unexpected lower-frequency response rather than simply disappearing. If the intended application or test conditions require it, bandwidth-limit the input spectrum so unwanted energy does not alias into the band being measured.
Clock feedthrough and output steps
Clock-related components may appear at the output and should not be mistaken for the desired filter response. TI’s MF10 data sheet describes clock-rate steps at the output and notes that a simple output RC low-pass can smooth them when appropriate. An RC network is not an automatic fix: it also changes the output path and may alter the response being measured. Decide whether the test is evaluating the IC output directly or the filtered system output, then document any added network.
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As broad family context, TI’s Basic Introduction to Filters—Active, Passive, and Switched-Cap, Rev. A says clock feedthrough on the order of 10 mV peak-to-peak can reach an output. This is not a guaranteed value for the device under test. The same overview gives typical switched-capacitor output noise of 100 to 300 μVrms over a 20 kHz bandwidth; use the individual part’s data sheet for device-specific noise limits.
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Clipping, gain changes, and offset
Reduce the signal amplitude if the output clips, particularly in a high-Q configuration where gain near the center frequency can exceed unity. TI warns in the MF10 data sheet that clipping changes gain and can also change fO and Q. An apparent corner or center-frequency error may therefore be caused by overload rather than a clock-ratio problem. Check for DC offset and compare the observed waveform with the device’s specified input and output swing.
Noisy or unstable readings
Separate noise in the measured result from noise intrinsic to the filter. Check the signal source, supply stability, grounding, probe placement, and instrument settings, and repeat measurements with the same conditions. TI’s overview gives general context that switched-capacitor filters can have more noise than conventional active filters, but its broad figures should not be assigned as a noise specification for a particular IC.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Troubleshoot discrepancies in a useful order
| Symptom | Checks to make |
|---|---|
| Corner, center, or notch frequency is wrong | Measure the clock at the IC pin; verify the clock mode and ratio; check resistor values and configuration; confirm the selected output and data-sheet response landmark. |
| Unexpected high-frequency response | Consider aliasing and input energy near or above half the sampling frequency; check for clock feedthrough and source bandwidth. |
| Clock-rate ripple or spikes at the output | Confirm the observed component is clock-related. If appropriate to the intended system, evaluate output filtering without obscuring the direct IC response. |
| Gain or measured frequency changes with signal level | Lower the input amplitude and check output clipping, offset, and high-Q gain. |
| No output or a response on an unexpected pin | Recheck the supply/reference wiring, selected section, mode pins, output assignment, and clock presence at the IC. |
| Readings vary between runs | Measure clock stability, then check supply, generator, grounding, probing, loading, and instrument resolution for repeatability. |
Change one condition at a time while troubleshooting. If the clock, input amplitude, resistor setting, and load all change together, a better-looking trace will not reveal which change corrected the problem.
Compare device claims without treating parts as interchangeable
Published ratios and accuracy figures help plan a test, but they cover different devices and conditions. They do not establish relative performance across every parameter. The table separates the facts available for these examples; consult each part’s documentation for its complete configuration and operating limits.
| Device | Function and frequency relationship | Published figures in the cited material | Bench implication |
|---|---|---|---|
| MF10-N | Dual universal second-order building block; separate high-pass/notch/all-pass, band-pass, and low-pass outputs. Center-frequency relationship depends on clock, mode, and in some configurations external resistor ratios. | TI product page lists ±0.6% clock-to-center-frequency ratio accuracy, 0 to 70 °C operating range, and operation up to 30 kHz. | Calculate from the selected configuration’s data-sheet equation. Its two sections can be cascaded for up to fourth-order functions, but the test must identify the section and output being measured. |
| TLC04 | Fixed-function fourth-order Butterworth switched-capacitor low-pass filter; 50:1 clock-to-cutoff ratio. | TI lists ±0.8% ratio error and a 0.1 Hz to 30 kHz cutoff range under the stated ±2.5 V supply condition. | Use the 50:1 relationship only for the TLC04 and verify the conditions and limits in its data sheet. |
| TLC14 | Separate fixed-function family example; 100:1 clock-to-cutoff ratio. | TI lists ±1% ratio error in the family information. | Do not transfer the TLC04 ratio or MF10-N configuration assumptions to the TLC14. |
For general context rather than a device guarantee, TI’s overview says typical center-frequency accuracy is about 0.2% for many switched-capacitor ICs, with worst-case figures ranging from 0.4% to 1.5% assuming an accurate clock. The same document’s noise and feedthrough figures are broad context, not acceptance limits. The Davies Sinusoidal Generator application note, dated October 2022, illustrates the TLC04 clocked at 50 times the desired corner in a tracking harmonic-filter use case. That example shows clock-based tuning; it is not a general bench acceptance procedure.
Define pass or investigate, rather than guessing
A useful test report states the measured response and conditions, then compares the result with the correct data-sheet specification. A defensible conclusion requires the actual device and configuration, a measured clock, stable supplies, documented input and load, a response landmark defined by the data sheet, and a measurement resolution adequate to evaluate the tolerance. If a result falls outside an expected range, first determine whether the mismatch comes from setup, response interpretation, or measurement uncertainty before treating it as a device failure.
Do not borrow a typical family accuracy figure as a guaranteed pass/fail limit. For example, TI’s broad “Basic Introduction to Filters” figure is explicitly conditional on an accurate clock and does not replace a particular IC’s guaranteed specification. Likewise, a product-page feature value should not be reported as though it accounts for clock-source error, instrument uncertainty, resistor tolerance, or all configuration-dependent effects.
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