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Firmware and PCB work can overlap before a finished board exists—but only after the team defines the hardware/software boundary well enough for each side to work against it. Set shared requirements, publish an interface contract and a minimal baseline, then divide tasks into parallel workstreams with scheduled integration points. This removes avoidable waiting; it does not remove dependencies or guarantee a particular schedule reduction.
Where parallel work helps—and where it cannot
In a strictly sequential process, firmware development waits for a board, while PCB design may wait for software requirements to settle. Some work does not need to wait: engineers can build firmware architecture and driver scaffolding against agreed interfaces while the hardware team develops the schematic and layout. Test planning and suitable simulation or modeling can proceed alongside both.
The overlap is useful only to the extent that the dependencies are understood. Firmware that depends on an unsettled pin assignment, register map, interrupt behavior, boot flow or peripheral choice may need rework when those decisions change. Hardware/software co-design treats allocation and trade-offs as joint system decisions, with objectives such as performance, power, cost and reliability considered together. IEEE Technology Navigator’s hardware/software co-design overview describes this concurrent approach and the role of interface specification and modeling.
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Define the contract before dividing the work
Before firmware and PCB contributors branch into separate tasks, agree on the requirements and boundary conditions they share. At minimum, identify the processor, key peripherals, external interfaces, expected behavior, timing constraints and relevant board assumptions. Treat hardware/software allocation as a joint design decision where practical, not as a one-way handoff that locks every choice prematurely.
Then record what firmware may rely on. IEEE’s overview specifically identifies registers, interrupts and memory maps as details that can be formally specified to support parallel work. For a board project, a useful contract will often also identify:
- Pin assignments and signals, including which details are fixed and which remain provisional.
- Bus and peripheral behavior, including expected operating modes and relevant timing assumptions.
- Boot and reset assumptions, memory organization and interrupt behavior.
- Interface or document revision identifiers, so a change can be tied to the firmware and board versions affected.
This list is practical guidance built on the interface-specification principle; it is not a claim that every project needs the same document format. The contract should be detailed enough for real work to start and explicit about unresolved decisions. If a critical choice changes, communicate the change and identify its consequences rather than allowing separate teams to keep using different assumptions.
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Build a baseline, then split work around dependencies
A baseline does not have to be a finished platform. AMD’s Embedded Design Development Using Vitis User Guide recommends a first iteration with minimal content sufficient to generate basic dependencies. In that Vitis workflow, AMD also recommends dividing work into roles and activities while preserving a forward, sequential flow for merging the work.
Apply the same principle to the project at hand: establish enough shared structure to make independent contributions possible, then give each contributor a clear scope and prerequisite. A typical division might look like this:
- Firmware: establish application structure and implement drivers or abstractions against the agreed interface. Mark behavior that depends on provisional hardware decisions.
- PCB design: develop the schematic and layout against the system requirements, documenting assumptions that affect software, such as pin use or peripheral connectivity.
- Verification: define test cases for the hardware/software boundary, including expected behavior, timing and failure conditions.
- Modeling or platform work: provide a simulator, virtual platform, RTL/software co-simulation setup, FPGA prototype or early platform where the project and toolchain support it.
These are example workstreams, not a prescribed team structure. The right split depends on actual skills, tools and dependencies. Assigning nominally parallel work that relies on unresolved shared decisions simply moves the wait into later integration.
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Start firmware before the final board when the artifacts support it
Firmware can begin before the final physical hardware is ready if its dependencies are defined well enough. Depending on the design, engineers may use a hardware abstraction layer, virtual platform, RTL/software co-simulation, FPGA prototype, written interface contract or early platform. These options do not offer identical fidelity: a written contract can support interface-level development, while a model or prototype can expose additional interaction problems. None should be treated as proof that the final board will behave exactly as expected.
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For an example of a product-specific workflow, Altium Resources states that its users can build schematics and PCB layout while an embedded team builds code, with project data tracked on a shared platform. That is a vendor description of its own product workflow, not independent evidence that a particular tool or platform will shorten every team’s schedule. Evaluate any workflow on whether it fits the existing ECAD and firmware toolchain and whether it keeps assumptions, revisions and handoffs visible.
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Make integration a controlled sequence
Parallel contributors still need a deliberate path back to one working design. AMD recommends sequential merging, a lead designer to synchronize contributor releases, and greater caution as a design matures. Its guidance is written for AMD Vitis embedded development, so the specific tool-flow details are not universal; the coordination principle is broadly useful.
Name an integration owner and agree on when contributions are brought together. The owner should know which interface version each contribution targets, coordinate release iterations and surface conflicts early. Avoid leaving all integration until the board is complete: that is when incompatible assumptions are most expensive to discover.
At each integration point, track the artifacts that must match. AMD’s version-specific Embedded Design Development documentation gives examples of hardware outputs such as an XSA and system device tree artifacts for software build flows, as well as firmware bundles and a hardware-to-OS handoff. Those artifacts apply to the documented AMD flow, not every PCB product. In a general board project, identify the firmware build, board revision, configuration and relevant test results together so that a reported behavior can be reproduced against the right combination.
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Verify across the hardware/software boundary
Passing separate firmware and PCB reviews is not enough if their interaction has not been checked. Test the boundary against the contract: do signals, registers, interrupts, buses, reset and boot assumptions behave as the software expects? Use the most representative artifact available at each stage, then repeat relevant checks on later hardware as it becomes available.
Models and early platforms can expose integration issues sooner, but their results are limited by what they represent. Keep track of which behavior was tested on a model, prototype or physical board, and do not treat a model-only pass as board validation. As the design approaches release, review interface changes more carefully and assess which firmware, PCB, configuration and tests need to be updated or repeated.
A practical readiness checklist
- Shared system requirements and major hardware/software allocation decisions are documented.
- The interface contract identifies current assumptions, open decisions and revision information.
- A minimal baseline gives contributors the dependencies needed to start.
- Each parallel task has a clear owner, scope and prerequisite.
- The team has chosen appropriate models or early artifacts and understands their verification limits.
- An integration owner, merge sequence and synchronization points are established.
- Firmware, board, configuration and test outputs can be associated with the revisions they cover.
- Interface changes receive review, with stricter control as the design matures.
Further reading
IEEE Technology Navigator: Hardware/Software Co-design provides conceptual background on concurrent design, interfaces, modeling and co-verification. For an AMD Vitis-specific example of baselines, team roles and integration, see AMD’s Embedded Design Development Using Vitis User Guide (UG1701), English 2026.1, released July 31, 2026. AMD’s Embedded Design Development documentation is version-sensitive; check that the release context matches the tool flow in use.
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