The Tool Desk
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Start by measuring the data path, not by changing a tuning flag. Use hardware counters, MPI traces, GPU profilers and I/O traces to determine whether the dominant stall is DRAM or HBM bandwidth, remote NUMA access, CPU-to-GPU movement, MPI communication, synchronization or storage throughput. Then keep data on the resource that uses it: bind ranks and threads, allocate memory on the nearest NUMA node, reduce transfers and tune the I/O layer your application actually calls.
This approach prevents a common failure mode in supercomputing optimization: improving one link while leaving the real bottleneck untouched. A huge-page setting cannot repair PCIe traffic, a faster filesystem cannot fix remote NUMA placement, and adding cores can make a memory-contended collective slower. The sections below provide a measurement-led sequence for finding and removing each class of bottleneck.
1. Classify the bottleneck before changing settings
Record a baseline on the same node type, process count, input size and software stack that you intend to optimize. Capture runtime and enough counters or traces to answer four questions:
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- Are loads going to a remote NUMA node or to memory attached to a different accelerator?
- How many bytes and messages cross CPU-GPU, GPU-GPU or network links, and how large is each transfer?
- Are processes waiting on MPI collectives, synchronization or filesystem operations rather than computing?
Classify the main stall as bandwidth saturation, access latency, transfer overhead, synchronization or I/O throughput. Keep the baseline, topology description and software versions with every run. Without that record, a change in affinity or page size can appear helpful simply because the job landed on a different set of cores.
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| Observed signature | Likely limiter | First experiment |
|---|---|---|
| High memory-controller traffic, low arithmetic utilization and little idle time | DRAM or HBM bandwidth | Change data layout, reuse and thread/rank placement; test fewer competing workers. |
| Large variation between otherwise identical runs; high remote-memory traffic | NUMA locality or page migration | Bind ranks and threads, use first-touch placement and test an explicit memory policy. |
| Long gaps around kernel launches or memcpy operations | CPU-GPU transfer overhead | Keep intermediates on the device and batch small transfers. |
| Processes spend time in MPI calls, especially collectives | Communication, synchronization or oversubscription | Map ranks to the topology and test rank count, thread count and collective behavior. |
| Low compute utilization while read/write time dominates | Parallel filesystem or I/O stack | Tune collective I/O, buffers and aggregators at the API layer in use. |
Do not infer a bottleneck from a single utilization percentage. A job can show moderate average bandwidth while suffering latency from remote accesses, or show low PCIe utilization while paying the fixed setup cost of thousands of tiny transfers.
2. Make CPU and accelerator memory local
Understand the NUMA topology
NUMA systems distribute physical memory among sockets or nodes. A core can access local memory with lower latency and higher effective bandwidth than memory attached to another socket. GPU-visible systems add another locality rule: the CPU NUMA node nearest a device is generally the best place for host buffers used by that device. Inspect the node, socket, core, hardware-thread and accelerator topology before selecting a mapping.
Automatic NUMA balancing can migrate pages while a GPU workload is running. NVIDIA’s guidance warns that this behavior can degrade performance or introduce run-to-run variation in GPU-visible NUMA configurations. Where measurement shows migration or instability, disable automatic balancing according to the system administrator’s policy and use an explicit placement policy instead.
Bind ranks, threads and allocations together
Rank placement, thread placement and allocation placement must describe the same ownership. A rank that is pinned to socket 0 but first-touches its arrays from socket 1 will repeatedly pay for remote access. Likewise, a GPU-fed buffer allocated on the NUMA node farthest from the GPU adds an avoidable hop before data reaches the device.
- Map the hardware topology and identify the NUMA node attached to each CPU socket and accelerator.
- Choose a rank-per-socket or rank-per-NUMA-domain layout that does not oversubscribe memory channels or interconnect links.
- Bind each rank and its worker threads to the intended cores or hardware threads.
- Initialize or first-touch arrays from the rank or thread that will use them. If the runtime allocates on demand, verify that its memory-affinity policy follows the requesting processor.
- Run an explicit memory policy when required. For example, a process that must allocate from node 0 can be launched with
numactl -m 0 ./app. Use the node number appropriate to the measured topology, not this example number by default. - Compare local and remote traffic counters and end-to-end runtime against the baseline.
Open MPI provides memory-affinity support so allocations are generally local to the processor requesting them, but the result still depends on how ranks and threads are mapped and when pages are first touched. Microsoft reports that explicit binding by NUMA node, core or hardware thread can scale better than default placement for HPC workloads.
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When fewer cores are faster
Adding workers does not create more memory bandwidth. If several ranks on a socket contend for the same channels, using fewer cores per cache or core complex can raise per-rank throughput. Microsoft has observed cases where fewer cores per CCX reduce memory-bandwidth contention and improve collectives such as MPI_Allreduce. Treat that as a workload-specific result: test several core counts while holding input, rank mapping and frequency policy constant.
3. Reduce CPU-to-GPU and GPU-to-GPU movement
Move computation to the data
Transfers have a fixed cost in addition to the time needed to move bytes. AMD’s HIP performance guidance recommends minimizing low-bandwidth host-device transfers, moving computation to the device when that avoids a round trip, and batching small transfers because every transaction incurs driver and PCIe setup overhead.
CUDA’s best-practices documentation gives an illustrative comparison from a V100 connected over PCIe Gen3: about 898 GB/s of device-memory bandwidth versus about 16 GB/s of host-device PCIe bandwidth. These are figures for that example architecture, not universal specifications for current systems. The implication is durable: device memory can be orders of magnitude faster than the link used to refill it, so an algorithm that repeatedly returns small intermediates to the CPU can be transfer-bound even when its kernels are efficient.
Keep intermediates resident
- Allocate input and working buffers on the device once, rather than recreating them for every operation.
- Chain kernels so an intermediate remains on the device. Do not copy it to the CPU merely to perform a small operation that could run on the accelerator.
- Batch independent small messages or copies into larger transfers when latency, ordering and memory limits permit.
- Copy results back only when the host or another device genuinely needs them.
- Measure both bytes transferred and transfer count. A lower byte total with thousands of tiny operations may still be slower than a slightly larger, well-batched transfer.
CUDA explicitly classifies minimizing host-device movement as a high-priority optimization, even when a kernel moved to the device does not beat its CPU version in isolation. Eliminating the round trip can still improve the complete pipeline.
Choose host memory deliberately
Pinned (page-locked) memory can support efficient asynchronous transfers, while managed memory and explicitly staged buffers can simplify programming or accommodate oversubscription. None is automatically faster. Compare transfer time, overlap, page faults and memory footprint on the target runtime. HPE documents that managed-memory pointer queries can add overhead on latency-sensitive MPI paths; validate managed-memory settings before using them in a communication-critical loop.
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For GPU-aware MPI, verify that the installed MPI and driver support the intended GPU IPC and registered shared-memory paths. Check registration behavior, IPC thresholds and managed-memory handling for the exact versions on the cluster. A setting copied from another installation can silently force staging through host memory.
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Make accesses contiguous and coalesced
Storage location, layout and access order can change achieved bandwidth dramatically. On CPUs, arrange hot fields and loop order to use cache lines efficiently and avoid unnecessary strided access. On GPUs, choose layouts and thread access patterns that produce coalesced transactions. Keep a working set in cache, shared memory or HBM when its reuse justifies the space.
- Prefer contiguous slices for the innermost loop where the hardware can stream them.
- Use a structure-of-arrays layout when separate fields are consumed by many parallel workers, and an array-of-structures layout when records are consumed together; benchmark both for the actual access pattern.
- Tile or block algorithms so data is reused from cache, shared memory or HBM before it is evicted.
- Align and size buffers according to the compiler, MPI and accelerator requirements in use.
- Eliminate redundant materialization of temporary arrays when a fused operation can consume a producer’s output directly.
Recompute when movement costs more
Transferring or loading a value is not always cheaper than calculating it again. CUDA’s guidance notes that recomputing a value can be faster than transferring it when arithmetic is inexpensive and the data path is congested. Compare the extra instructions with the saved bytes and synchronization; do not apply recomputation to expensive or numerically sensitive work without checking correctness and precision.
5. Tune MPI communication and collectives
Map ranks to links and memory
Place ranks so that frequent neighbors share the shortest available path, while avoiding oversubscription of a socket’s memory channels or an interconnect link. Keep ranks that use a particular accelerator near its associated CPU NUMA node. Confirm the mapping in MPI startup output or a topology tool rather than assuming rank order matches physical order.
Separate communication time into message latency, injected bandwidth, synchronization and memory-copy components. A job with many tiny messages needs a different remedy from one sending a few large messages. Aggregating messages can reduce per-message latency, but excessive aggregation can delay progress or increase memory use.
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Test rank and thread counts as a coupled choice
Increasing MPI ranks while leaving the same number of threads per rank changes memory pressure, cache sharing and collective algorithms. Run a small matrix of rank counts, thread counts and bindings. Include the production collective pattern, not just a point-to-point microbenchmark. In some memory-bound applications, fewer ranks per socket deliver more useful bandwidth; in others, additional ranks hide latency.
Validate GPU-aware paths
When MPI receives a device pointer, determine whether the library performs direct GPU IPC, uses registered host memory or stages through an internal buffer. Registration limits, IPC thresholds and managed-memory behavior vary by MPI and driver version. Confirm the path with the MPI’s diagnostic options or profiling tools, and compare it with an explicitly staged implementation. Keep the version and launch configuration in the benchmark record because a cluster upgrade can change the selected protocol.
6. Tune parallel I/O at the layer your application uses
Recognize the I/O stack
High-level libraries such as H5py and HDF5 may issue MPI-IO operations, which in turn use POSIX filesystem calls. NERSC describes this as a layered stack. Tune the layer that directly controls the behavior you observe: changing a POSIX hint will not necessarily fix an HDF5 datatype conversion or an H5py access pattern.
| Application path | Measurements to collect | Experiments |
|---|---|---|
| H5py or HDF5 | Dataset layout, chunk accesses, datatype conversions and time in library calls | Use the library’s collective or independent mode appropriately; remove unnecessary conversions and align chunking with the access pattern. |
| MPI-IO | Collective versus independent calls, request sizes, aggregators and filesystem time | Test collective reads/writes, buffer sizes and aggregator counts; inspect ROMIO collective-buffering parameters. |
| POSIX or a custom I/O layer | Read/write sizes, concurrency, metadata calls and server-side throughput | Adjust application buffering and concurrency only after confirming that the lower layer is the limiter. |
Use collective I/O deliberately
Collective I/O coordinates calls from many processes and can combine noncontiguous requests into larger operations. Test it against independent I/O for the actual file layout, process count and filesystem. The useful aggregator count depends on the storage system and job shape; more aggregators are not automatically faster.
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For MPI-IO, vary collective-buffer sizes and aggregator counts one at a time, then test the best combination under production concurrency. NERSC cautions that old data-sieving hints can interfere with collective buffering. Remove or isolate those hints when collective operations are enabled, and verify the resulting access pattern rather than assuming a legacy setting remains beneficial.
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Control metadata and conversion overhead
Many small file operations, frequent metadata updates and datatype conversions can dominate sustained bandwidth. Consolidate logically related data where the format and recovery requirements permit, use an access pattern that matches dataset chunking, and profile conversion time before changing filesystem parameters. A faster storage target cannot compensate for an application that repeatedly converts the same data in user space.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.7. Evaluate huge pages and executable placement conditionally
Huge pages
Huge pages represent more memory with fewer page-table entries. That can lower translation overhead and sometimes improve cache behavior for memory-intensive MPI applications. NERSC specifically reports that huge pages can reduce access cost in workloads with many MPI_Alltoall operations; HPE likewise documents lower page-table overhead and possible cache benefits.
Huge pages consume reserved memory and can hurt portability or allocation success when the pool is fragmented. Enable them only on nodes configured to provide the required pages, and compare page faults, translation misses, memory bandwidth and end-to-end runtime with standard pages. A benefit in an all-to-all-heavy workload does not establish a benefit for a streaming stencil or an I/O-bound job.
Copy executables into node memory when startup is the issue
Tools such as sbcast can copy an executable into node-local memory before launch. That may shorten startup and reduce run-to-run variation when many nodes read the same binary from shared storage. It does not increase sustained DRAM or HBM bandwidth and therefore will not repair a steady-state memory bottleneck. Measure launch time separately from application runtime before adopting it.
8. Run controlled optimization experiments
Use a small, repeatable experiment plan instead of changing several controls at once. Microsoft recommends tuning for the specific workload; the same binding or core-count choice can help one application and harm another.
- Freeze the software stack, input, node type, frequency policy and process count.
- Record topology, rank/thread mapping, memory policy, page size, transfer counts, MPI protocol and I/O settings.
- Change one variable or one tightly related pair, such as rank binding plus first-touch placement.
- Run enough repetitions to expose placement and filesystem variability. Report median and spread, not a single best run.
- Check that the intended path was actually used: local versus remote memory, direct versus staged GPU transfers, collective versus independent I/O.
- Keep a change only when it improves the production metric without violating memory capacity, correctness, portability or operational constraints.
| Decision axis | Questions to ask |
|---|---|
| Locality | Does data stay on the local NUMA node, socket-attached HBM or nearest accelerator? |
| Movement | How many bytes and individual transfers cross CPU-GPU, GPU-GPU or network boundaries? |
| Granularity | Are messages and copies large enough to amortize fixed setup overhead? |
| Concurrency | Do ranks and threads oversubscribe cores, memory channels or links? |
| I/O semantics | Are operations independent or collective, and are buffers and aggregators sized for the filesystem? |
| Portability and cost | Will the setting work on CPU-only, GPU and heterogeneous nodes without fragile site-specific assumptions? |
9. Troubleshoot by symptom
Runtime changes from one identical run to the next
- Check automatic NUMA balancing, page migration and first-touch order.
- Confirm that ranks and threads are bound rather than allowed to drift.
- Compare node allocation, neighboring jobs and filesystem load.
- Use explicit NUMA placement when measurements show remote access, then retest variability.
GPU kernels are fast but the application is slow
- Count host-device copies and kernel-launch gaps, including transfers hidden inside a library.
- Keep intermediates on the device and fuse or batch small operations.
- Verify that host buffers are appropriate for asynchronous transfers and that MPI is not staging device data unexpectedly.
- Compare the complete pipeline, not isolated kernel timings.
Adding cores lowers throughput
- Inspect memory-channel saturation and cache or CCX contention.
- Test fewer cores per CCX or fewer ranks per socket.
- Recheck collective time, especially
MPI_Allreduce, under each mapping. - Ensure that extra threads are not competing for the same data or oversubscribing the interconnect.
Parallel writes scale poorly
- Determine whether the application calls HDF5, MPI-IO or POSIX directly.
- Compare collective and independent operations with measured request sizes.
- Vary collective-buffer sizes and aggregator counts.
- Remove data-sieving hints that conflict with collective buffering, then measure metadata and conversion costs separately.
10. A practical order of operations
For most memory- and transfer-bound jobs, apply changes in this order:
- Profile and classify the dominant stall on the production topology.
- Bind ranks and threads and establish first-touch or explicit NUMA placement.
- Eliminate unnecessary CPU-GPU round trips and batch the transfers that remain.
- Fix layout, access order and reuse so each loaded byte does more work.
- Retune MPI rank and thread counts, collectives and GPU-aware communication paths.
- Tune collective I/O, buffers and aggregators at the HDF5, MPI-IO or POSIX layer actually used.
- Benchmark huge pages or executable staging only when the measurements point to translation or startup overhead.
- Document the winning configuration, its topology assumptions and the conditions under which it was measured.
There is no universal percentage improvement for these techniques. The useful result is a demonstrated reduction in remote bytes, transfer count, synchronization time or I/O wait on the target application and topology. Treat every setting as a hypothesis, verify the path it changes, and keep the one that improves the full workload rather than an isolated microbenchmark.
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