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Do not connect a TTL video signal to an RP2350 GPIO until you have identified the exact pin, confirmed whether it is standard or fail-safe-tolerant (FT) IO, measured the source waveform, and checked the RP2350’s power sequence. At an IOVDD of 3.3 V, standard IO has an absolute-maximum pin voltage of IOVDD + 0.5 V (3.8 V), while an FT pin can tolerate up to 5.5 V only when IOVDD is present. Neither rating is a blanket approval for every 5 V signal, every package pin, or an unpowered board.
The safe answer depends on the pin and the waveform
“5 V TTL video” describes a source loosely, not a complete electrical specification. Before choosing a connection, determine the source’s actual minimum and maximum voltage, polarity, overshoot and undershoot, edge rate, source impedance, timing or bandwidth requirements, and whether it continues driving while the RP2350 is off. A signal called TTL may be a unipolar digital waveform, a sync stream, or a video-related signal with ringing and negative excursions. Those cases do not impose the same stress on a GPIO.
The RP2350 datasheet also distinguishes standard IO from FT IO. The classification is pin-specific and package-specific; two pins on the same device cannot automatically be treated alike. Read the pin table for the exact RP2350 variant and package, then verify the board’s IOVDD rail and the selected input-threshold configuration.
If the pin is standard IO, a direct 5 V connection is outside its 3.3 V operating range and can exceed its absolute maximum. If it is a verified FT pin, the 5.5 V rating is conditional: IOVDD must be present. When the RP2350 is unpowered, the FT absolute maximum falls to 3.63 V, so an externally powered 5 V source can still be unsafe.
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RP2350 voltage limits you must interpret correctly
Raspberry Pi’s current RP2350 Datasheet electrical specifications, accessed in 2026, separate functional input specifications from stress limits. A functional threshold tells you what voltage the input is guaranteed to recognize. An absolute maximum tells you a stress boundary that should not be exceeded; it is not a recommended signal level or a design target.
| IO category or condition | Documented value | What it means for a TTL-video connection |
|---|---|---|
| Standard IO absolute maximum | -0.5 V to IOVDD + 0.5 V | At IOVDD = 3.3 V, the upper stress limit is 3.8 V. Expected peaks should be kept below this with margin; do not design a waveform to touch the limit. |
| Standard input-high functional specification at IOVDD = 3.3 V | 2 V minimum high threshold; input voltage in the functional table up to IOVDD + 0.3 V | A signal can be recognized as high above 2 V, but that does not authorize a 5 V level or replace the absolute-maximum check. |
| FT IO absolute maximum at IOVDD = 3.3 V, with IOVDD present | -0.5 V to 5.5 V | A verified FT pin may accept a positive input as high as 5.5 V under this powered condition, subject to the pin’s other specifications and the source waveform. |
| FT input-high functional specification at IOVDD = 3.3 V | 2 V to 5.5 V | The input-high range extends to 5.5 V only under the datasheet’s conditions. The 2 V threshold is not a guarantee that arbitrary video edges or transients are harmless. |
| FT IO absolute maximum at IOVDD = 2.5 V | 4.2 V | The allowable external voltage changes with IOVDD; do not reuse the 3.3 V figure at another rail voltage. |
| FT IO absolute maximum at IOVDD = 1.8 V or 0 V | 3.63 V | A 5 V source is above the stated limit when the rail is 1.8 V or absent. |
| Digital IO supply | Nominally 1.8 V to 3.3 V | Input limits and threshold behavior depend on the actual IOVDD setting. |
The FT high-level specification includes an important condition: IOVDD must be powered to tolerate an input above 3.63 V. This is why “the pin is 5 V tolerant” is incomplete. It must be “this exact FT pin, at this IOVDD voltage, while that supply is present, and with the source staying within the specified range.”
The datasheet also warns: Using IOVDD voltages greater than 1.8V, with the input thresholds set for 1.8V may result in damage to the chip.
Select threshold settings that match the rail and the intended interface; do not assume a threshold mode is harmless merely because the logic signal is digital.
Why a TTL video waveform can be more dangerous than its nominal voltage
Nominal high voltage is only one number
A source advertised as 5 V TTL may produce a high level near 5 V, but the RP2350 pin experiences the complete waveform. Cable reflections, connector inductance, fast output drivers, and poor termination can create short overshoot peaks. A multimeter may show a safe-looking average while an oscilloscope reveals excursions beyond the pin limit.
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Negative excursions matter too
Both standard and FT tables show a lower absolute limit of -0.5 V under the stated conditions. Video-related signals can ring below ground at transitions or include intentionally negative sync components. A passive divider scales a negative excursion but does not make an unbounded or severe negative transient safe. If the measured waveform crosses the allowed range, use an interface designed for bipolar or transient-prone signals rather than assuming a series resistor is protection.
Power-off behavior can invalidate an otherwise acceptable connection
Consider every state: RP2350 powered and running, booting, held in reset, IOVDD ramping, and completely off while the video source remains on. The FT 5.5 V allowance requires IOVDD to be present, and the FT limit at IOVDD = 0 V is 3.63 V. A source that is safe during normal operation can therefore become unsafe during startup, shutdown, unplugging, or a board fault.
Identify the receiving pin before selecting an interface
- Record the exact device and package. Use the RP2350 variant and package fitted to your board, not a generic GPIO diagram.
- Find the pin in the datasheet. Confirm whether it is standard IO or FT IO. If the classification is not explicit, treat the pin as not verified for 5 V.
- Confirm IOVDD. Measure or obtain the rail voltage in normal operation and during power-up, reset, shutdown, and any low-power mode that leaves the source connected.
- Check input-threshold configuration. Make sure the selected threshold mode is appropriate for IOVDD. Pay particular attention to the datasheet’s warning about using 1.8 V thresholds with an IOVDD above 1.8 V.
- Check whether the pin has another electrical function. Alternate functions, boot straps, analog functions, and board-level pull-ups can change loading and startup behavior even when the pin is used as a digital input.
Do not infer FT capability from the connector voltage, from another RP2350 board, or from a neighboring pin. The receiving pin’s documented classification controls the decision.
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Obtain the source datasheet where possible. If the specification is unclear, measure the signal at the point where the interface will connect, using an oscilloscope probe with suitable bandwidth and grounding. Capture the slowest and fastest transitions, the highest positive peak, the lowest negative peak, and behavior when the RP2350 board is switched off.
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- Voltage: record the guaranteed minimum and maximum, not only the nominal 5 V label.
- Polarity: establish whether logic-low or sync is below ground, inverted, or otherwise unusual.
- Overshoot and undershoot: measure peaks at the connector and at the proposed GPIO node, including cable and termination effects.
- Edge rate: fast edges can produce ringing and may require controlled impedance or a buffer even when the logic frequency is modest.
- Source impedance and drive state: determine whether the source is push-pull, open-drain, terminated, or still driven while the RP2350 is off.
- Timing: verify that any divider, filter, or level translator preserves the pulse width, rise time, and video timing the software expects.
If you cannot obtain or measure these characteristics, you do not yet have enough information to approve a direct connection or choose exact resistor values.
Choose among direct connection, a divider, and an active interface
Direct connection
A direct connection is appropriate only when the entire source waveform is within the exact pin’s functional and absolute limits for every relevant power state. For a standard IO pin at IOVDD = 3.3 V, a 5 V TTL high does not meet that requirement. For an FT pin, direct connection still requires IOVDD to be present, a source peak no higher than the applicable limit, acceptable negative behavior, and compatible timing and loading.
Because the title alone does not establish those conditions, “use an FT pin” is a verification step, not a universal wiring instruction.
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Resistor divider for a bounded positive signal
A divider is a possible interface when the source is unipolar, its maximum voltage is known, its source can tolerate the added load, and the resulting waveform remains fast and clean enough for the input. For a top resistor from the source to the GPIO node and a bottom resistor from that node to ground:
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VGPIO = VSOURCE × Rbottom / (Rtop + Rbottom)
Calculate the ratio from the source’s worst-case high voltage, then check the actual GPIO voltage against the receiving pin’s documented functional range and a conservative margin below its absolute maximum. Also calculate the source current and include the GPIO input leakage, board pull resistors, probe loading, and any downstream protection capacitance. The divider’s Thevenin resistance and pin capacitance determine edge rate.
For illustration only, if a source could reach 5.0 V and you wanted approximately 3.0 V before loading, a ratio of 0.60 would give that ideal unloaded value. That arithmetic is not a recommended circuit: the correct ratio depends on the source tolerance, measured overshoot, IOVDD, pin classification, resistor tolerances, and required timing. Exact resistor values cannot be selected from “5 V TTL video” alone.
A divider does not solve negative voltage, an unpowered-board condition, severe overshoot, or an incompatible source impedance. Add a separate protection or active-interface design when those conditions exist.
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Use an active buffer or level shifter when the source and RP2350 use different logic domains, the cable is long or noisy, the divider would distort edges, the source must be isolated during power-off, or the signal has polarity and protection requirements beyond a passive network. Select the part from its own datasheet. Check input-voltage range, output levels at the RP2350’s IOVDD, direction control, propagation delay, edge rate, fail-safe or power-off behavior, supply sequencing, and whether it tolerates the source’s negative or transient excursions.
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Purpose-built transient or negative-voltage protection
If the measured waveform leaves the GPIO’s allowed range, use a protection/interface circuit designed for the actual amplitude, duration, repetition rate, and source impedance. A series resistor can limit current in some fault cases, but it does not by itself guarantee that the pin voltage remains within its limits. Do not treat a generic clamp or a resistor as a substitute for checking the protected node under worst-case conditions.
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- Define the operating states. Write down IOVDD during normal operation, boot, reset, shutdown, and complete power loss. Include whether the video source can be powered independently.
- Classify the pin. Confirm standard or FT IO in the exact datasheet pinout. If unverified, do not apply the FT limits.
- Measure the source. Capture maximum positive and negative peaks, overshoot, edge rate, frequency, duty cycle, and behavior with the RP2350 off.
- Set the allowable GPIO envelope. Use the functional threshold for logic recognition and stay comfortably inside the absolute-maximum limits. At 3.3 V IOVDD, do not confuse the 2 V high threshold with permission to apply 5 V to standard IO.
- Select the interface topology. Choose direct connection only if every condition is documented; choose a divider for a bounded positive source that can tolerate its loading; choose an active or protected interface for level, polarity, transient, timing, or power-sequencing problems.
- Calculate worst-case values. Include source tolerance, resistor tolerance, loading, leakage, overshoot, and IOVDD variation. Check both high and low levels and the resulting rise and fall times.
- Prototype with current limiting and measurement access. Bring the interface up at reduced risk, monitor the GPIO node with an oscilloscope, and test source-on/RP2350-off and RP2350-on/source-off transitions.
- Verify logic and stress margins. Confirm that the RP2350 consistently recognizes the intended video timing while the measured node remains inside the documented range in every tested state. If the waveform is outside the range, stop and redesign rather than relying on software filtering.
Common mistakes and how to correct them
| Mistake | Why it fails | Correction |
|---|---|---|
| Assuming every RP2350 GPIO is 5 V tolerant | Standard and FT IO have different limits, and the classification is pin-specific. | Check the exact package pinout and datasheet electrical table. |
| Using the 5.5 V FT number while IOVDD is off | The 5.5 V condition requires IOVDD to be present; at IOVDD = 0 V the FT limit is 3.63 V. | Guarantee source isolation or use an interface with documented power-off behavior. |
| Treating the 2 V high threshold as a voltage limit | A threshold is a functional recognition point, not an absolute-maximum rating. | Apply both the functional table and the absolute-maximum table, with margin. |
| Choosing a divider from nominal values only | Tolerance, overshoot, loading, and edge-rate effects can raise the GPIO peak or corrupt timing. | Use worst-case calculations and measure the node under real cable and load conditions. |
| Ignoring negative ringing | A divider scales but does not eliminate negative excursions. | Measure undershoot and select a protection/interface designed for it. |
| Leaving the source connected during shutdown without testing | Power sequencing can change the applicable limits and create an unsafe powered-input condition. | Test all source and RP2350 power combinations or add isolation. |
| Changing IOVDD or threshold settings casually | The datasheet warns that using thresholds for 1.8 V with IOVDD above 1.8 V may damage the chip. | Keep threshold selection consistent with the actual IOVDD and documented configuration. |
What to document before building
- RP2350 variant, package, board revision, and exact receiving pin.
- Standard or FT classification and the datasheet revision used.
- IOVDD voltage in every power state.
- Source minimum, maximum, polarity, overshoot, undershoot, impedance, and drive state.
- Chosen interface topology and worst-case voltage calculations.
- Measured GPIO-node waveform, including startup and power-off tests.
- Logic-threshold configuration and video timing requirements.
Keeping these records prevents a later board revision, alternate RP2350 package, or different video source from silently invalidating the interface.
Bottom line for a 5 V TTL-video source
For an unverified standard RP2350 IO, do not connect a 5 V TTL-video signal directly. A verified FT pin can have a 5.5 V absolute maximum at IOVDD = 3.3 V, but only with IOVDD present and only for a waveform that meets the other limits. With the RP2350 unpowered, the FT limit is 3.63 V, so power sequencing remains part of the protection design. Use a calculated divider only for a known, positive, bounded source whose loading and timing you have checked; use an active or purpose-built protected interface when the waveform includes negative excursions, transients, long-cable ringing, or unsafe power states.
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