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Estimate an LLM accelerator in four passes: calculate model-weight bytes, calculate KV-cache bytes for the longest context and concurrent sequences, subtract runtime allocations and safety headroom from usable device memory, then compare the workload’s data movement with the accelerator’s on-device memory bandwidth. The result is a planning estimate, not a guarantee of fit or tokens per second. Exact model architecture, quantization, tensor-parallel sharding, serving runtime and scheduling settings must be validated in the intended deployment.
What you are actually sizing
An inference server must hold more than the model’s checkpoint. Device memory is consumed by several categories at the same time:
- Weights: the parameters loaded from the checkpoint, in the selected precision.
- KV cache: keys and values retained for every active sequence and every token in its context.
- Runtime allocations: activations, temporary tensors, communication buffers, CUDA graphs, attention workspaces, adapters and other framework-managed memory.
- Feature reservations: space for multimodal inputs, hybrid-model state or other optional capabilities enabled by the runtime.
NVIDIA documents these additional consumers in its NIM GPU-memory troubleshooting guide and TensorRT-LLM describes weights, activation tensors, runtime buffers and KV-cache pools in its memory documentation. A card that appears large enough for the checkpoint can still fail during startup or when a longer request arrives.
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Capacity and speed are separate questions. A device can have enough memory to load a model but insufficient bandwidth for the desired decode rate, or ample bandwidth but too little capacity for the target context and concurrency.
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Collect the model and workload inputs first
Write down these values before doing arithmetic. Use the model configuration and checkpoint metadata rather than a rounded marketing name wherever possible.
- Total parameter count.
- Weight precision: BF16, FP16, FP8, INT4, NVFP4 or another format.
- KV-cache precision, which can differ from weight precision.
- Number of transformer layers.
- Attention-head count, KV-head count and head dimension.
- Maximum input context, maximum generated output and the resulting cache length.
- Maximum simultaneous sequences or scheduler batch size.
- Tensor-parallel degree and any pipeline or expert sharding.
- Runtime features such as LoRA adapters, multimodal processing, CUDA graphs and paged-cache settings.
For sizing, the cache length normally includes prompt tokens plus generated tokens that remain resident. A request advertised as “128K context” therefore needs enough cache for the actual prompt and output allowance selected by the serving configuration, not merely the average prompt.
Step 1: Estimate model-weight memory
The first-order formula
Use:
weight bytes per GPU ≈ total parameter count × bytes per parameter ÷ tensor-parallel degree
For rough planning, NVIDIA’s NIM guidance uses the following bytes-per-parameter assumptions:
| Weight format | Planning value | What the value represents |
|---|---|---|
| BF16 | 2 bytes | Two bytes per stored parameter for the heuristic calculation |
| FP16 | 2 bytes | Two bytes per stored parameter for the heuristic calculation |
| FP8 | 1 byte | One byte per stored parameter for the heuristic calculation |
| INT4/NVFP4 | 0.5 byte | Half a byte per stored parameter for the heuristic calculation |
These values estimate payload storage, not the complete allocation. Quantization scales, metadata, padding, tensor-parallel layout and checkpoint format can add memory, while implementation details can change how tensors are packed. NVIDIA recommends basing the estimate on the parameter count or checkpoint metadata; see the NIM memory guide.
Worked weight examples
- 8B model in BF16: 8 billion × 2 bytes is approximately 16 GB of weights. NVIDIA uses this as an illustration for fitting an 8B model on a 24 GB GPU, including an RTX 4090 example. The remaining nominal capacity is not all available to KV cache because runtime allocations also need space.
- 70B model in BF16 across four GPUs: 70 billion × 2 ÷ 4 is approximately 35 GB of weight storage per GPU before other allocations.
- 70B model in FP8 across two GPUs: 70 billion × 1 ÷ 2 is approximately 35 GB per GPU before other allocations.
The two 70B examples have the same first-order per-device weight number but different precision, GPU count and communication requirements. They are not interchangeable deployments: FP8 support, accuracy, calibration and runtime kernels must be verified, and sharding determines how much communication occurs.
Why the arithmetic can be wrong in practice
A parameter-count calculation can understate memory when the checkpoint includes quantization metadata, replicated tensors or alignment padding. It can also overstate the memory available to the application if the device reserves space for the driver or runtime. Treat the result as a filter that rules out obviously undersized configurations, then confirm actual startup allocation in the target serving stack.
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General per-token formula
For a common transformer architecture, NVIDIA gives:
KV bytes per token = 2 × number of layers × (number of KV heads × head dimension) × bytes per cache element
The factor of two accounts for keys and values. If the model’s attention-head count multiplied by head dimension equals its hidden size, this is often written as:
total KV bytes ≈ batch size × sequence length × 2 × number of layers × hidden size × bytes per cache element
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Use the first form when the model uses multi-query attention (MQA), grouped-query attention (GQA) or another layout in which the number of KV heads differs from the total attention-head count. Substituting hidden size without checking KV-head dimensions can substantially overestimate or underestimate the cache.
Apply batch and context
Multiply the per-token value by the number of resident tokens:
KV-cache bytes ≈ simultaneous sequences × cache length per sequence × KV bytes per token
Cache memory therefore grows linearly with both concurrency and context. Doubling the maximum sequence length doubles the cache reservation at the same batch. A scheduler that admits more sequences can exhaust memory even when every individual request fits.
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Reference calculations
NVIDIA’s inference-optimization article gives a Llama 2 7B example with 32 layers, hidden size 4096, a 4096-token sequence, batch one and FP16 cache. Using the common formula produces roughly 2 GB of KV cache. The figure is an illustration of the scaling relationship, not a universal value for every 7B model. Read the full explanation in Mastering LLM Techniques: Inference Optimization.
A separate NVIDIA example estimates that Llama 3 70B in FP16 uses approximately 140 GB for weights and approximately 40 GB of KV cache for a 128K-token, single-user context. That is about 180 GB before runtime allocations. NVIDIA notes that the cache figure scales linearly with the number of users in that example; model-specific KV dimensions and cache format still matter. The example appears in Accelerate Large-Scale LLM Inference and KV Cache Offload with CPU-GPU Memory Sharing.
Cache precision and architecture choices
Reducing cache precision reduces the cache payload, but it is an independent decision from weight quantization. A model with FP8 weights can still use an FP16 cache, and a BF16 model can use another supported cache format. Validate numerical quality and kernel support with the selected runtime.
GQA and MQA store fewer KV heads than a conventional multi-head-attention layout. Mixture-of-experts models may have a large total parameter count but activate only a subset of experts per token; that affects compute and data movement, while the exact stored weights and cache layout still determine capacity. Use the configuration’s actual layer, KV-head and head-dimension fields rather than inferring them from the model family name.
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After calculating weights and cache, reserve memory for everything the runtime allocates around them. NVIDIA lists activations, communication buffers, CUDA graphs, LoRA adapters, multimodal reservations and hybrid-model state as possible consumers in its NIM guidance. TensorRT-LLM separately accounts for weights, activation tensors, runtime buffers and KV-cache pools in its memory-usage reference.
There is no universal overhead percentage that applies to every model, GPU, runtime version or feature set. Framework defaults also control how remaining memory is divided into cache pools and temporary workspace. Do not promise a fixed “10% reserve” or assume that all advertised gigabytes are allocatable by the model.
A practical capacity equation
For planning, think in terms of:
usable model budget = device memory − runtime allocations − deliberate safety headroom
Then require:
weight memory + KV-cache reservation ≤ usable model budget
Keep the headroom explicit. It protects against allocator fragmentation, variable-length requests, graph capture changes, adapter loading and small differences between a dry run and production traffic. The correct amount must be measured for the chosen stack; the cited NVIDIA documentation does not establish a universal reserve.
Worked capacity scenarios
8B BF16 on a 24 GB device
The weight heuristic gives approximately 16 GB. That leaves roughly 8 GB on the nominal specification before the driver, runtime buffers, activations and cache are considered. A short-context, low-concurrency service may fit, while a long-context or highly concurrent service may not. The 24 GB device is an example used by NVIDIA to explain weight fit, not a guarantee of production capacity.
70B BF16 on four devices
The first-order weight estimate is approximately 35 GB per device. Add the model’s sharded KV cache and runtime allocations to each device’s share. The cache may not divide identically to the weights, depending on the attention implementation and parallelism strategy, so inspect per-device allocations rather than multiplying a single-device estimate by four and assuming perfect balance.
70B FP8 on two devices
The heuristic is again approximately 35 GB per device for weights. This can reduce the number of devices compared with BF16, but only if the accelerator and serving runtime support the chosen FP8 path and the model’s quality target is met. KV-cache precision and context limits still determine whether the configuration fits.
70B with a 128K single-user context
Using NVIDIA’s illustrative figures, approximately 140 GB of FP16 weights plus approximately 40 GB of KV cache already totals about 180 GB. Runtime allocations and headroom come on top. This example demonstrates why very long context can dominate capacity even when concurrency is one.
Separate prefill from decode when estimating speed
Memory capacity answers “will it fit?” Bandwidth helps answer “how quickly can it generate?” NVIDIA distinguishes two phases in Mastering LLM Techniques: Inference Optimization:
- Prefill: processes the prompt’s tokens in parallel. It tends to use substantial arithmetic and benefits from parallel matrix operations.
- Decode: generates output autoregressively, usually one token at a time. Each step reads model state and grows or consults the KV cache.
For decode, NVIDIA explains that weights, keys, values and activations must be transferred and concludes: “In other words, this is a memory-bound operation.” That statement describes the phase qualitatively; it is not a benchmark or a promise of achieved tokens per second.
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A first-order bandwidth ceiling
For a rough intuition, divide effective memory bandwidth by the bytes that must be moved for each generated token:
idealized tokens per second ≈ effective bandwidth ÷ bytes moved per generated token
In a simple low-batch thought experiment, model weights are a major recurring movement cost and KV reads increase with active context. For example, dividing 3.35 TB/s by 80 GB gives about 41.9 token-equivalents per second if an entire 80 GB weight set were moved once per generated token. That is an idealized arithmetic ceiling, not a measured result: real kernels do not achieve peak bandwidth continuously, and batching, cache reuse, memory locality, communication, scheduling and arithmetic all change the outcome.
Do not turn peak bandwidth into a guaranteed service-level objective. Measure time to first token (often prefill-sensitive), inter-token latency (decode-sensitive), throughput at the target concurrency and tail latency under realistic request lengths.
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Capacity and bandwidth can differ within one product family. NVIDIA’s H100 specifications list these two variants:
| Variant | GPU memory | GPU memory bandwidth | Interpretation |
|---|---|---|---|
| H100 SXM | 80 GB | 3.35 TB/s | Manufacturer specification for the SXM module |
| H100 NVL | 94 GB | 3.9 TB/s | Manufacturer specification for the NVL variant |
These values come from NVIDIA’s H100 GPU specifications. The same page lists GPU-to-GPU interconnect specifications separately. Do not confuse interconnect bandwidth between accelerators with the on-device memory bandwidth used to read local HBM.
What to compare between candidate configurations
| Axis | Question to answer |
|---|---|
| Capacity | Does each device have enough usable memory for its weight, cache and runtime allocation? |
| On-device bandwidth | Can the memory subsystem move the decode working set at the required latency? |
| Precision | Are the selected weight and KV formats supported, accurate enough and implemented efficiently? |
| Sharding | How are weights, KV blocks and expert layers divided across devices? |
| Interconnect | Can cross-device traffic sustain the tensor- or pipeline-parallel schedule? |
| Context and concurrency | What maximum cache length and number of active sequences must be admitted? |
| Runtime behavior | How much memory do graphs, workspaces, adapters and cache pools reserve? |
| Measured service metrics | What are time to first token, inter-token latency, throughput and tail latency at production-like loads? |
A specification-only comparison cannot establish a deployment winner. The workload’s context distribution, batching policy and runtime implementation can reverse the apparent advantage of a card with more memory or higher peak bandwidth.
A repeatable sizing workflow
- Extract configuration values. Record parameter count, layer count, hidden size, attention-head count, KV-head count, head dimension, weight precision and cache precision.
- Define the service envelope. Set maximum prompt length, maximum output allowance and simultaneous sequences. Convert them into the cache length used by the runtime.
- Choose parallelism. Set tensor-parallel degree and any pipeline or expert strategy, then calculate the per-device weight estimate.
- Calculate KV cache. Use KV heads × head dimension when the architecture differs from the common hidden-size assumption. Multiply by layers, two for keys and values, bytes per cache element, sequences and cache length.
- List non-model allocations. Include activations, communication buffers, CUDA graphs, adapters, multimodal reservations, workspaces and any hybrid-model state enabled in production.
- Check capacity per device. Subtract measured or documented runtime allocations and explicit headroom from physical memory. Compare that usable budget with the per-device weights and cache.
- Compare bandwidth. Estimate the decode working set and use the accelerator’s exact on-device bandwidth specification as a first-order ceiling, not a promise.
- Build the intended engine. Launch the exact model, precision, runtime version, parallelism and scheduler settings in a representative environment.
- Inspect startup and profile logs. Record actual weight allocation, cache capacity, graph/workspace reservations and per-device balance.
- Load-test the envelope. Test realistic prompt and output distributions, target concurrency, cache reuse, batching and failure behavior. Adjust limits if measured headroom is insufficient.
Diagnose common sizing failures
The model fails before serving starts
Verify the checkpoint’s real parameter count and precision, then compare actual per-device weight allocation with the tensor-parallel calculation. Check whether tensors are replicated, whether quantization metadata is present and whether the runtime reserved graph or workspace memory. A lower cache limit cannot fix a configuration whose weights alone exceed usable device memory.
Startup succeeds but long requests fail
The cache envelope is too large for the remaining budget. Confirm that cache length includes prompt and output tokens, check maximum simultaneous sequences and inspect whether the scheduler reserves a pool for the configured maximum rather than the current average. Reduce context, concurrency or cache bytes per element only when those changes are acceptable for quality and runtime support.
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Inspect sharding and replicated tensors. Tensor parallelism does not guarantee identical allocations for every cache or workspace. Look for uneven KV-head placement, pipeline-stage differences, adapters loaded on one rank or a communication buffer sized by the largest stage.
Memory fits but decode is slow
Measure inter-token latency separately from prompt processing. A fit check says nothing about memory traffic efficiency. Investigate achieved bandwidth, kernel selection, batching, KV-cache locality, cross-device communication and scheduler delays. Compare the measured result with the workload’s target rather than with peak bandwidth alone.
Changing precision produces an unexpected result
Weight precision and cache precision are separate. A smaller checkpoint may leave the KV cache unchanged, while a cache-format change may require different kernels or alter numerical behavior. Confirm both allocations and quality under the exact runtime build.
Capacity, bandwidth and cost decisions
Once the per-device requirement is known, infrastructure choices generally fall into a single-device deployment, a multi-device server or an accelerator instance rented from a cloud provider. Select among them using required usable memory, on-device bandwidth, interconnect, power and measured workload performance. A larger device can reduce sharding complexity; multiple smaller devices can provide capacity but add communication and operational overhead.
Capacity arithmetic alone cannot establish cost per million tokens. That economic result also needs acquisition or rental price, utilization, power or instance billing, preprocessing overhead, batching efficiency and achieved tokens per second. Without those measurements for the target model and service envelope, a price claim would be speculative.
Quick Recap
Final validation checklist
- Parameter count and checkpoint metadata are recorded.
- Weight and KV-cache precisions are identified separately.
- Layer count, KV-head count and head dimension come from the model configuration.
- Prompt length, output allowance and concurrent sequences reflect the production limit.
- Weights and KV cache are calculated per device after the planned sharding.
- Runtime allocations and deliberate headroom are included rather than hidden in a percentage guess.
- The exact accelerator variant’s memory and on-device bandwidth are used.
- Interconnect bandwidth is treated separately from local GPU memory bandwidth.
- Startup logs confirm real allocations and cache capacity.
- Load tests measure time to first token, inter-token latency, throughput and tail behavior at target concurrency.
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