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Compare foundries against your chip’s requirements, not by node number alone. Verify the exact process version and production status, then evaluate design enablement, specialty features, packaging, capacity, geography, support, yield, cost and lead time using evidence for your own design. TSMC, Samsung Foundry and Intel Foundry have overlapping leading-edge offerings but materially different portfolios and published milestones; no public source establishes a neutral ranking of their yields, prices or delivery performance.
What a foundry comparison must establish
A semiconductor foundry manufactures wafers and often supplies the process design kit (PDK), libraries, intellectual-property (IP) options, design-rule documentation, engineering support and packaging path needed to turn a customer’s design into a tested product. The right supplier is therefore the one that can repeatedly build your chip, in the required package and volume, within its electrical, schedule and commercial constraints.
Start by writing a one-page requirement sheet before contacting suppliers. Include logic and memory content, target power-performance-area (PPA), die size, package and bandwidth, operating temperature, reliability and qualification standards, expected annual volume, ramp date, acceptable manufacturing locations and supply-continuity requirements. A process that looks attractive on a slide can be unsuitable if it lacks an IP block, embedded memory, high-voltage devices, radio features, automotive qualification or the package your system needs.
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Classify every claimed milestone as development, announced target, risk production or high-volume production (HVM). Development and roadmap dates indicate intent; risk production means an early manufacturing phase used to discover and correct problems; HVM indicates regular production, but does not guarantee capacity for a new customer. Ask what experience applies to the exact process variant, transistor option, voltage range and package in your design.
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Treat node names as vendor labels
“N2,” “SF2” and “18A” are names for different process generations. They do not prove equal transistor dimensions, density, power, performance or product results. Even within one supplier, a process family can have variants with different design rules, libraries, SRAM options, analog devices and voltage capabilities. Require measured PPA from a port of your design, with the same RTL, implementation constraints, IP assumptions, operating conditions and yield target, before making a node-based decision.
Published positions of the three foundries
| Foundry | Published portfolio or scale evidence | Leading-edge status reported by the company | What the statement does not prove |
|---|---|---|---|
| TSMC | Describes a dedicated pure-play foundry model, advanced logic, specialty processes, manufacturing and design support, and the 3DFabric family of 3D silicon stacking and advanced-packaging solutions. Its 2025 annual report says it manufactured 12,682 products for 534 customers using 305 distinct technologies. | N2 entered HVM in the fourth quarter of 2025; TSMC expects a fast ramp in 2026. A14 is described as a future generation with volume production scheduled for 2028. | The product, customer and technology counts are scale indicators, not a guarantee of yield, customer satisfaction, available slots or pricing for a particular design. The A14 date is a company schedule, not a completed milestone. |
| Samsung Foundry | Describes a logic portfolio from 180 nm to 2 nm and beyond, plus specialty technologies including embedded non-volatile memory (eNVM), radio-frequency (RF), CMOS image sensors (CIS), high-voltage (HV) and BCD processes. | Samsung says SF2, its second-generation MBCFET/GAA node, started mass production in 2025 and targets mobile, high-performance computing, artificial intelligence and automotive applications. | These are Samsung-reported capabilities and timing. They do not establish comparative yield, wafer price, cycle time or capacity allocation. |
| Intel Foundry | Promotes Intel process technologies and packaging. The 18A product material describes RibbonFET gate-all-around transistors, PowerVia backside power delivery and advanced integration options; Intel also describes a public Foundry Shuttle multi-product wafer program for prototyping. | Intel’s June 2026 newsroom update says 18A entered production in 2025 and 18A-P entered risk production. Intel’s product page states that 18A is in HVM in the United States. | Intel’s published performance figures are comparisons with Intel 3 baselines, not a like-for-like ranking against TSMC or Samsung. Shuttle eligibility and service details require confirmation for each project. |
TSMC: broad pure-play scale and advanced packaging
TSMC positions itself as a dedicated pure-play foundry: it manufactures products designed by customers rather than selling its own branded system chips. In its 2025 annual report, it reports 12,682 products for 534 customers across 305 distinct technologies. Those figures show a very broad manufacturing and technology portfolio, but they cannot predict the outcome of an individual tape-out.
TSMC reports that technologies at 7 nm and smaller generated 74% of its 2025 wafer revenue, compared with 69% in 2024. This is TSMC’s own wafer-revenue definition and should not be compared directly with another company’s node-mix statistic, which may use different categories or accounting periods.
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TSMC says N2 entered HVM in the fourth quarter of 2025 and expects a fast ramp during 2026. For a design scheduled before that ramp is established, request a written capacity and yield plan rather than assuming that HVM status means immediate availability. TSMC describes A14 as a future generation with volume production scheduled for 2028. Treat that as a target date when building a product plan; maintain a fallback process if your launch depends on it.
3DFabric and multi-die designs
TSMC’s 3DFabric family covers 3D silicon stacking and advanced packaging. For chiplet, stacked-memory or high-bandwidth systems, compare the complete path: die-to-die interface IP, interposer or substrate, bonding method, thermal limits, known-good-die flow, test insertion, package yield and total cost. A front-end node advantage can disappear if the required package is unavailable, unqualified or too expensive at your volume.
Samsung Foundry: logic plus explicit specialty options
Samsung Foundry describes a portfolio that spans mature 180 nm technology through 2 nm and beyond. Its specialty list is important when a product needs more than dense digital logic: eNVM for embedded code or configuration, RF devices for wireless circuitry, CIS for image capture, HV devices for power management and BCD integration for mixed bipolar, CMOS and DMOS functions.
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SF2 production claim
Samsung says SF2, its second-generation MBCFET/GAA process, began mass production in 2025 and is aimed at mobile, HPC, AI and automotive applications. Ask which SF2 option applies to your voltage, memory, reliability and package requirements, and ask for the maturity data behind the exact design rules and IP set you would use. “Mass production” is a company-reported status; it is not evidence that every design type has the same yield or that capacity is uncommitted.
When Samsung’s specialty portfolio changes the decision
If your chip combines digital logic with image sensing, radio, high voltage or embedded memory, a process with those devices integrated and qualified may reduce die count, package complexity and software or calibration work. Compare the resulting system bill of materials and qualification schedule with a smaller logic node that would require separate companion dies. Conversely, do not select a specialty process merely because it is available: check its density, speed, leakage, memory endurance, analog performance and long-term supply plan against your requirements.
Intel Foundry: 18A, backside power and a U.S. production path
Intel’s 18A materials describe RibbonFET gate-all-around transistors and PowerVia backside power delivery. Intel’s June 2026 update says 18A entered production in 2025 and 18A-P entered risk production. The 18A product page states that 18A is in HVM in the United States. Confirm which facility, package flow and capacity reservation apply to your product; a national footprint or public HVM statement does not itself reserve wafers for a new customer.
Interpreting Intel’s published performance figures
Intel publishes performance figures against Intel 3 baselines. Such internal comparisons can show the intended improvement between Intel generations, but they are not a direct TSMC-versus-Samsung-versus-Intel benchmark. For a fair comparison, port the same design or a representative block through each candidate’s available PDK and implementation flow, then measure PPA, timing closure effort, leakage and achieved yield under identical assumptions.
Foundry Shuttle for early exploration
Intel describes a public Foundry Shuttle as a multi-product wafer program for design prototyping on leading-edge technologies. It may lower the barrier to an early test chip, but confirm current eligibility, schedule, mask or participation fees, die-size limits, test access, packaging options and the path from shuttle results to dedicated production. Do not treat participation in a shuttle as a production commitment.
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Compare process maturity and design enablement first
For each candidate process, request a dated checklist and record the answer for the exact variant:
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- PDK release, design-rule stability and sign-off status.
- Standard-cell, SRAM, I/O, analog, RF, HV, eNVM, CIS and security IP availability.
- EDA-tool versions, certified flows, reference designs and support response times.
- Required design-rule waivers, reticle limits, mask schedule and expected engineering-change policy.
- Silicon-learning, first-silicon and production-yield data for designs with similar density, die size and voltage mix.
Separate “available” from “qualified for your use.” A library may exist but lack automotive qualification; an IP block may be licensed but not characterized at your temperature range; a PDK may be downloadable while late rule changes remain likely. These differences affect schedule and engineering cost as much as transistor density.
Match specialty requirements instead of defaulting to the newest node
Leading-edge logic is usually justified by a specific PPA or integration need. A mature or specialty node can be superior when the design includes high-voltage interfaces, precision analog, radio, image sensors, embedded non-volatile memory, large non-digital macros or stringent operating-temperature requirements.
| Design need | Questions for every foundry | Decision signal |
|---|---|---|
| Digital compute or AI | What density, frequency, voltage and SRAM options are available? How much of the target workload has been implemented on this exact variant? | Choose the flow that closes timing and power with acceptable yield and package bandwidth, not the smallest label. |
| RF or mixed signal | Are RF devices, passive models, isolation rules and calibration IP integrated in the same process? | An integrated specialty process may avoid a second die and difficult package interfaces. |
| Image sensing | Is CIS available with the required pixel, optical, dark-current and readout characteristics? | Compare sensor performance and qualification, not just logic density. |
| Power management or automotive interfaces | Are HV and BCD devices, reliability models and temperature qualifications available? | A mature qualified process can reduce risk versus porting those functions to an advanced logic node. |
| Embedded code or configuration | Does eNVM meet endurance, retention, security and test requirements at the planned temperature? | Integrated eNVM may simplify the system, provided capacity and qualification are sufficient. |
Evaluate packaging, chiplets and 3D integration as one system
For a single small die, front-end wafer cost and PPA may dominate. For multi-die systems, packaging can determine bandwidth, latency, thermal performance, reliability and total cost. Ask each supplier to map your architecture to a complete qualified flow:
- Die-to-die protocol and PHY IP, including interoperability and test coverage.
- 2.5D interposer, fan-out, hybrid bonding or 3D stacking options.
- Known-good-die definition, wafer sort, package assembly and final-test insertion.
- Thermal interface, warpage, power delivery and mechanical reliability limits.
- Package-level yield model and ownership of failures between wafer, assembly and test.
TSMC identifies 3DFabric as its 3D stacking and advanced-packaging family. Intel’s 18A-PT material describes advanced 3D integration. These public descriptions establish that both companies address advanced integration, but they do not provide a neutral comparison of package yield, cost or delivery. Obtain project-specific quotations and qualification plans.
Check capacity, geography and supply resilience
Public announcements about fabs or national manufacturing footprints do not prove that a particular process has an available slot when your product ramps. Ask for the manufacturing site or sites, wafer-start allocation, substrate and assembly dependencies, expansion assumptions, business-continuity plan and change-notification terms.
Geography can matter for export controls, customer requirements, logistics, disaster recovery and tax or incentive conditions. Define whether wafers, packaging and test must remain in a particular region. If a second source is required, determine whether the alternate uses the same IP, package, mask set and qualification evidence or requires a full redesign.
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Request comparable commercial and operational evidence
The reviewed public material does not establish a cross-company dataset for yield, wafer price or delivery lead time. Those numbers are customer- and design-specific. Ask every finalist for the same evidence and define each metric before scoring:
| Metric | Evidence to request | How to normalize it |
|---|---|---|
| Yield | Learning-curve data and mature-production yield for comparable die size, defect sensitivity, memory and analog content. | State whether it is wafer sort, final test, gross or net yield, and the date and volume behind it. |
| Cost | Mask, wafer, shuttle, IP, engineering, package, test and NRE charges. | Use the same forecast volume, die size, package, exchange-rate assumption and amortization period. |
| Cycle time | Typical and committed wafer, assembly and test lead times, including queue assumptions. | Separate pilot, ramp and steady-state production; record escalation and expedite terms. |
| Capacity | Written allocation by site, node and quarter, plus trigger points for expansion. | Distinguish installed capacity from capacity reserved for your program. |
| Quality and support | Reliability data, qualification plan, issue-response targets and named technical interfaces. | Compare obligations in the contract, not informal assurances. |
Do not convert one supplier’s best-case benchmark into a forecast for another supplier’s design. Require confidence ranges, assumptions and a definition for every number.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.A repeatable foundry-selection procedure
- Freeze the requirements. Document PPA targets, specialty devices, memory, package, temperature, qualification, volume, ramp date and geography.
- Shortlist technically eligible processes. Eliminate any candidate lacking a required device, IP block, package, voltage range or production date.
- Verify maturity. Label each candidate as development, roadmap, risk production or HVM for the exact variant, and record the evidence date.
- Run equivalent design studies. Use the same representative RTL, constraints, IP assumptions and sign-off criteria. Measure achieved PPA, implementation effort, leakage and memory results.
- Model the package and system. Include die-to-die links, memory bandwidth, thermal solution, assembly yield, test and total cost.
- Request written capacity and commercial terms. Obtain wafer allocation, cycle time, price structure, mask and NRE fees, quality commitments and change-control terms.
- Score with weighted criteria. Set weights before reviewing supplier-specific claims; keep a separate confidence rating for measured, committed and roadmap data.
- Plan qualification and fallback. Define shuttle or test-chip gates, production-qualification lots, second-source strategy and the decision date for switching processes.
Common comparison mistakes and how to avoid them
Ranking by the smallest node number
Node names are not a universal ruler. Replace a headline ranking with design-specific PPA, IP readiness, yield evidence and schedule risk.
Counting a roadmap as available capacity
A future-generation production date is not a wafer reservation. Obtain a committed ramp plan and retain a proven fallback.
Mixing incompatible statistics
TSMC’s 74% 2025 wafer-revenue share from 7 nm and smaller technologies cannot be compared directly with a different company’s process mix. Align definitions, periods and denominators before using any statistic.
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Ignoring specialty functions
A dense logic node may require separate analog, RF, sensor or power dies. Include those dies, packages, software and qualification in the system comparison.
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Treating internal benchmarks as independent tests
Intel’s 18A figures against Intel 3, and every other supplier’s own benchmark, are useful for understanding that company’s claims but are not neutral cross-vendor measurements.
Assuming HVM means guaranteed delivery
HVM status says nothing about your allocation, assembly bottleneck or lead time. Put capacity, escalation and delivery assumptions in the commercial plan.
How to make the final decision
Choose the foundry with the strongest evidence across the full product path, not the supplier with the most impressive single node. A sensible decision record should show: the exact process and status; measured PPA and design effort; required specialty devices and IP; package and integration plan; site and capacity commitment; normalized cost and lead time; qualification and quality obligations; and the fallback if a milestone slips.
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The winning choice is the one that can demonstrate, for your design and launch window, a credible path from PDK and first silicon through qualified package, allocated capacity, predictable yield and contractual delivery.
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