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Choose a silicon MOSFET for the converter role and its worst-case operating point—not by the lowest advertised RDS(on) alone. First set a safe VDS(max) above the highest bus voltage and measured spike, then balance temperature-adjusted conduction loss, switching loss, gate-drive loss, reverse-recovery behavior, package parasitics and cooling. A high-side hard-switching FET usually favors low QG and QGD; a synchronous low-side FET often favors a different balance of RDS(on), QOSS and body-diode QRR.
1. Define the MOSFET’s job and the real operating envelope
The same converter may need two very different MOSFETs. In a synchronous buck, the high-side control FET blocks the input voltage and switches the inductor current at high voltage and high frequency. The low-side synchronous FET carries current for much of each cycle and may conduct through its body diode during dead time. A primary switch in an isolated converter or a secondary rectifier has yet another loss balance.
Write down the worst case before looking at part numbers. Record the following values for the exact operating mode you are designing:
- Maximum and minimum input voltage, including startup, shutdown and load-dump or other system transients.
- Output voltage, maximum load current and inductor ripple current. Analog Devices cites 10% to 60% peak-to-peak ripple as a general design range.
- Switching frequency. Many high-current step-down supplies operate from about 100 kHz to 1 MHz, with some designs extending toward 2 MHz.
- Duty cycle at the high- and low-line corners.
- Ambient temperature, available airflow, PCB copper area and allowable MOSFET junction temperature.
- Gate-driver supply voltage, peak source/sink current, common-source inductance and the intended dead time.
- Measured or conservatively estimated switch-node overshoot, ringing and drain-current slew rate.
Use RMS current for conduction calculations, not simply the average load current. Ripple, duty cycle and current sharing can make the MOSFET RMS current materially different from the output-current rating.
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2. Set the voltage rating without paying for unnecessary resistance
VDS(max) must exceed the highest voltage the drain can actually see: the maximum bus voltage plus switching overshoot and ringing. Use the measured switch-node waveform on the real board when possible. If the waveform is not yet available, include a conservative transient allowance and verify it with a probe that has a short ground connection.
A higher voltage class is not automatically safer in the complete design. Silicon MOSFETs with a larger voltage rating commonly have higher RDS(on) for a given die area, which raises conduction loss. Analog Devices gives a practical example: with a 16 V maximum input, a 25 V or 30 V MOSFET can be appropriate, whereas choosing a 60 V part may add resistance without useful margin if the transient environment does not require it.
Voltage-rating checklist
- Calculate maximum bus voltage + worst-case spike, not nominal input voltage.
- Check the MOSFET’s avalanche and repetitive-avalanche specifications if the topology can force unclamped energy into the device.
- Confirm that the gate rating, usually specified separately from VDS, is compatible with the driver and any Miller-induced gate excursion.
- After assembly, measure drain-source voltage at the highest input voltage, maximum load and hottest expected operating condition.
3. Calculate conduction loss with hot RDS(on)
The basic MOSFET conduction estimate is:
Pcond = IRMS2 × RDS(on)(TJ)
Infineon states this same relationship in its synchronous-rectification guidance. Use the datasheet’s resistance at the gate voltage you will actually apply, then increase it for junction temperature. A value specified at 25 °C can be substantially lower than the resistance at the intended operating temperature.
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For a high-side buck FET, conduction occurs mainly during its duty-cycle interval, so calculate the RMS current over that interval, including inductor ripple. For a low-side synchronous FET, the conduction interval is approximately the complementary duty cycle, minus dead time, and the current waveform includes the same ripple. Parallel FETs require attention to layout and thermal symmetry; nominally identical devices can share unevenly when source inductance or copper resistance differs.
Why the lowest resistance may lose
A larger die can reduce RDS(on) while increasing total gate charge. At high frequency, that extra charge raises driver and transition losses. Select the resistance that meets the thermal and efficiency budget after all losses are included, rather than minimizing one datasheet line item in isolation.
4. For a high-side hard-switching FET, prioritize switching behavior
During each hard-switched transition, drain voltage and drain current overlap. The resulting energy is dissipated on every cycle, so switching loss rises with switching frequency. Infineon describes the relationship directly: switching losses grow in proportion to switching frequency because frequency is the repetition rate of the switching events.
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The most useful high-side parameters are usually total gate charge (QG), Miller charge (QGD), gate resistance, output charge (QOSS) or output energy (EOSS), and the package’s common-source and drain inductance. Lower QG and especially lower QGD can shorten the Miller plateau and reduce the time spent in the high-voltage/high-current overlap region, provided the driver can supply the required current.
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- Conduction: use
IRMS2 × RDS(on)with temperature-adjusted resistance. - Gate drive:
Pgate = QG × VG × fSW. Infineon notes that the average gate-drive current is equal toQG × fSW. - Hard switching: estimate transition energy from the actual voltage, current and rise/fall times, then multiply by switching frequency. Datasheet charge values help compare parts, but the converter’s driver, layout and load-line conditions determine the final result.
- Dead-time and diode loss: include the interval in which the body diode conducts before the opposite FET turns on.
Do not compare QG values measured at different drain voltages, currents or gate voltages as though they were interchangeable. Use the datasheet test conditions and, for finalists, test devices with the same driver and gate resistance.
5. Select a synchronous low-side FET by its complete commutation loss
The low-side synchronous FET has a different optimum from the high-side switch. Its low RDS(on) can dominate because it carries substantial RMS current, but its output capacitance and body-diode recovery also affect the opposite switch’s transition.
Texas Instruments identifies a useful synchronous-rectifier figure of merit involving RDS(on) × (½QOSS + QRR). It captures the trade-off between resistive loss and the charge that must be moved or recovered during commutation. Compare candidates using the same operating voltage and current; a low charge value at a different test condition is not an apples-to-apples advantage.
Body-diode and dead-time loss
During dead time, the inductor current commutates through the low-side body diode. Infineon’s synchronous-rectification example reports typical body-diode conduction times of 50 to 100 ns, while real applications can show 20 to 100 ns and current slew rates up to 800 A/µs. Diode loss depends on forward drop, current, conduction time and switching frequency.
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1Scan for outdated or missing drivers - takes under a minute2Repair Windows errors before they cause bigger problems3Fix the driver behind crashes, sound loss and screen glitchesExcessive dead time increases diode conduction loss. Insufficient dead time risks shoot-through when both MOSFETs conduct at once. Optimize dead time on the assembled converter while observing the gate signals and switch node at the highest current and temperature. Account for driver propagation mismatch, temperature drift and the MOSFET’s turn-off tail; the controller’s nominal dead-time setting is not the voltage-to-voltage interval at the device pins.
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6. Match the gate driver to the MOSFET
A MOSFET’s gate is a charge-controlled load. The driver must move QG quickly enough at the selected gate voltage, and it must sink charge rapidly during turn-off. Infineon’s relationship, IG,avg = QG × fSW, gives the average current; the peak current during the Miller plateau is set by the driver voltage, gate resistance and the MOSFET’s plateau voltage.
- Verify the driver’s source and sink current, output impedance and supply-voltage range.
- Use the datasheet’s total and Miller charge at the intended drain voltage and drain current.
- Check the absolute maximum gate-source voltage and the driver’s turn-on voltage. A MOSFET specified at 10 V may have significantly higher resistance at 4.5 V or 2.5 V.
- Place the driver close to the gate and use a compact gate-return path. Kelvin-source packages can separate the gate-return reference from the high-current source path.
- Choose gate resistance experimentally: too little resistance can produce ringing and false turn-on; too much increases transition loss.
At high frequency, gate-loop inductance can erase a low-charge part’s theoretical advantage. Measure the gate voltage directly at the MOSFET pins, not only at the driver output.
7. Treat package and PCB layout as electrical components
Package inductance adds voltage according to V = L × di/dt. In a converter with fast current edges, even a small common-source or drain-loop inductance can create overshoot, ringing and extra switching loss. It can also couple the power transition into the gate and cause unintended turn-on.
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Layout checks before approving a part
- Minimize the hot loop formed by the input bypass capacitor, high-side MOSFET and low-side current path.
- Keep the gate loop short and separate from the high-current commutation loop.
- Provide the package’s recommended copper area and thermal vias; do not assume the nominal package thermal resistance applies to a smaller board.
- Probe the switch node with a low-inductance spring or differential probe. A long oscilloscope ground lead can create a false ringing waveform.
- Recheck overshoot after changing package, copper geometry, gate resistor, input capacitor placement or switching frequency.
8. Check thermal limits at the real ambient temperature
The usable MOSFET is the one that stays below its junction-temperature limit after conduction, switching, gate-drive and diode-related losses are added. Start with the thermal path from junction to case or board, then include the specified board copper, vias, airflow and ambient temperature. A low-resistance device that runs hotter can end up with more resistance and less efficiency than a higher-resistance alternative with a better package or cooling path.
Calculate a first estimate as TJ = TA + Ploss × θJA for a board-mounted device, using the thermal resistance and board conditions that match your construction. For a case-cooled package, use the complete junction-to-case, interface and heat-sink path. Recalculate resistance at the resulting junction temperature, because the initial loss estimate and temperature are coupled.
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Infineon’s package choices include leadless, top-side-cooled and leaded options for different thermal requirements. Device families span low-voltage classes such as 55–200 V and higher-voltage silicon families aimed at 600–800 V automotive SMPS/DC-DC applications; select the class from the measured bus and transient requirement, not from the family name.
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- Identify the role. Mark each candidate position as high-side control FET, low-side synchronous FET, primary switch or secondary rectifier.
- Build the worst-case table. Enter maximum input, duty cycle, load current, inductor ripple, transient overshoot, ambient temperature and switching frequency for every operating corner.
- Set the voltage class. Choose VDS(max) above the bus-plus-spike value with a deliberate margin. Reject parts that depend on an unverified clamp or an optimistic transient estimate.
- Filter by gate compatibility. Confirm gate-voltage rating, specified RDS(on) at your drive voltage and the driver’s source/sink capability.
- Calculate conduction loss. Use the MOSFET RMS current and temperature-adjusted RDS(on) for each role and duty-cycle corner.
- Estimate switching and gate loss. Include QG, QGD, QOSS/EOSS, transition overlap, gate-drive voltage and frequency.
- For synchronous rectifiers, add recovery and dead-time terms. Compare QRR, output charge and body-diode forward loss at the same commutation conditions.
- Check the package and thermal path. Verify inductance, copper-area recommendations, thermal resistance, current capability and assembly constraints.
- Prototype the finalists. Keep the gate driver, gate resistor, layout and thermal boundary conditions identical so the comparison is meaningful.
- Measure before release. Capture gate-source voltage, drain-source overshoot, switch-node ringing, dead-time diode conduction and component temperature at every worst-case corner.
10. Compare candidates on one decision sheet
| Criterion | What to record | Why it matters |
|---|---|---|
| Voltage margin | VDS(max), measured peak drain voltage, avalanche data | Prevents breakdown while avoiding unnecessary resistance from an oversized voltage class. |
| Conduction | Hot RDS(on), RMS current, duty cycle | Determines the dominant resistive loss, especially in a synchronous low-side FET. |
| Switching charge | QG, QGD, test voltage and current | Sets gate-drive demand and affects hard-switching transition time. |
| Output charge and recovery | QOSS/EOSS, QRR, body-diode data | Controls commutation loss and is particularly important for synchronous rectification. |
| Driver compatibility | Gate rating, recommended drive voltage, source/sink current | Ensures the FET reaches low resistance and turns off without excessive delay or ringing. |
| Package and layout | Lead inductance, common-source inductance, thermal pad and recommended copper | Parasitics can create overshoot, false turn-on and additional transition loss. |
| Thermal capability | Relevant θ values, board or heat-sink conditions, junction limit | Determines whether the calculated loss is survivable at the actual ambient temperature. |
| Supply and qualification | Availability, lifecycle status, qualification and cost | A technically efficient part is not a production solution if it cannot be sourced or qualified. |
11. Worked comparison method (illustrative)
Suppose two 30 V candidates are being considered for a 16 V-input synchronous buck. The 30 V class is only acceptable after the measured switch-node peak confirms that the transient remains below the rating with margin; the nominal 16 V input alone is not sufficient evidence. For each candidate, calculate hot conduction loss from its RMS current and resistance at the actual gate voltage, then add the high-side transition and gate-drive terms. For the low-side position, include its complementary-duty conduction loss, body-diode loss during measured dead time, and the commutation contribution represented by ½QOSS + QRR.
If the lower-resistance candidate has substantially higher QG and QGD, it may win at a lower frequency but lose at 1 MHz. Conversely, a low-charge candidate can lose thermally if its resistance rises sharply at the operating junction temperature. Build the comparison with the same driver, gate resistor, input capacitors, PCB and cooling, then choose the part with the lowest measured total loss while retaining voltage and thermal margin.
12. Common selection failures and how to correct them
Choosing by RDS(on) alone
Symptom: The data-sheet resistance looks excellent, but efficiency falls as frequency rises. Correction: add gate-drive and switching loss, especially QG and QGD, and re-evaluate at the hot resistance.
Using the nominal bus voltage as the voltage rating
Symptom: Drain overshoot approaches or exceeds the MOSFET rating during a load step. Correction: measure the real switch node, shorten the hot loop, improve input bypassing or snubbing, and select a voltage class that still has margin after the correction.
Applying a high-side rule to the synchronous FET
Symptom: A low-QG low-side part runs hotter than a higher-charge alternative. Correction: compare low-side candidates using hot RDS(on), QOSS, QRR, body-diode drop and dead-time loss.
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Trusting an optimistic dead-time setting
Symptom: Efficiency changes sharply with temperature or the switch node shows shoot-through spikes. Correction: probe both gates at the pins, account for driver mismatch and propagation delay, and tune dead time while checking diode conduction and cross-conduction.
Ignoring the package
Symptom: The schematic simulation looks clean, but the prototype rings and the gate waveform oscillates. Correction: use a lower-inductance package or tighter layout, add a Kelvin source where available, and retune the gate resistor with short measurement connections.
Comparing charge numbers from incompatible tests
Symptom: The “better” datasheet part performs worse on the board. Correction: compare values at matching voltage, current and gate-drive conditions, then validate finalists with board measurements. Texas Instruments cautions that some QRR and QOSS values are less reliable than direct, apples-to-apples measurements.
13. The practical decision rule
For a high-frequency high-side hard switch, first meet the transient voltage requirement, then favor the lowest total loss using low QG/QGD, acceptable QOSS, and a package and driver that preserve a clean transition. For a synchronous low-side switch, first meet the voltage and thermal requirements, then weigh hot RDS(on) against QOSS, QRR, body-diode conduction and dead time. In both positions, the winning MOSFET is the one that delivers the lowest measured total loss with verified voltage, gate and junction-temperature margin in the finished converter.
Frequently Asked Questions
What matters more at high frequency: RDS(on) or gate charge?
Neither number wins universally. At high frequency, gate-drive and switching losses increase with frequency, while conduction loss follows RMS current squared times hot RDS(on). Choose the part with the lowest combined loss for the specific role and operating point.
How much voltage margin should a DC-DC MOSFET have?
Its VDS(max) must exceed the highest measured or conservatively estimated bus voltage plus switching overshoot. Use the smallest voltage class that provides verified margin, because unnecessarily high voltage ratings can increase RDS(on).
Why can a synchronous-rectifier MOSFET need different specifications from the high-side MOSFET?
The low-side device carries substantial RMS current and participates in commutation through its output capacitance and body diode. RDS(on), QOSS and QRR therefore need to be evaluated together rather than applying the high-side low-gate-charge preference.
What should I measure on the first prototype?
Measure gate-source voltage at each MOSFET, drain-source peak voltage and ringing, dead-time diode conduction, switch-node transitions and MOSFET temperature at maximum input, load and ambient conditions.
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