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Choose storage by role, not by interface name. Keep the active model state, execution buffers, and latency-critical data in accelerator memory and DRAM. Use NVMe SSDs for persistent models, datasets, and capacity tiers, adding SSD offload or caching only when measurements show that the software path helps. Treat historical Z-NAND/Z-SSD products as a specialized low-latency flash tier that requires current availability and support checks, and treat Samsung’s zNAND-O as a development concept rather than a retail option.
The storage decision in one sentence
AI inference works best as a hierarchy: accelerator memory is closest to computation, host DRAM supports the active working set and staging, and NVMe storage holds persistent data. Moving a tensor, model shard, or cache down that hierarchy increases capacity but normally adds latency and reduces effective bandwidth. A fast SSD can reduce model-load time or support carefully designed offload, but it does not become DRAM because it uses PCIe or NVMe.
The right choice depends on what is slow in your serving path. A model that already fits in accelerator memory has a different storage problem from a large model that must be loaded for every request, a retrieval system reading many small files, or an edge device with limited DRAM. Measure the complete path—from the application through the host and controller to the accelerator—before buying a specialized flash product.
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Active model weights and execution state
Weights and intermediate buffers used on every inference step are the most latency-sensitive data. They should reside in the accelerator’s memory whenever the model, batch size, context length, and concurrency allow it. If some state must be staged through the host, DRAM is the next working-memory tier. SSD space is capacity for this state, not an equivalent replacement for it.
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KV cache and other growing working sets
Long-context generation and concurrent sessions can make the key-value cache grow beyond the memory available for a single request. Decide whether to reduce context, batch size, or concurrency, use a cache-management policy, or test an explicit offload design. An SSD may hold colder portions in some software stacks, but the benefit depends on transfer size, access pattern, queue depth, and how often data returns to the accelerator.
Model loading and checkpoint staging
Persistent model files normally live on NVMe. The SSD is read when a process starts, a model is swapped, or a new shard is needed. Once loaded, the model should remain in accelerator memory or DRAM if the latency target requires it. Improving the storage tier can shorten startup and reload events without changing per-token latency after the working set is resident.
Retrieval data, feature stores, and datasets
Embedding indexes, tokenizer files, feature tables, and evaluation datasets are usually persistent. Their access pattern determines whether a conventional capacity-oriented SSD is sufficient or whether a lower-latency enterprise device and more DRAM caching are justified. Random reads under concurrency can behave very differently from a sequential model load, so test the real request mix.
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How the tiers differ
| Tier | Best-supported role | What to investigate | Limitations and checks |
|---|---|---|---|
| Accelerator memory and host DRAM | Active working set, execution state, model weights in use, and latency-sensitive data | Capacity, memory bandwidth, placement, and transfer path to the processor | Capacity and cost limits; exact performance depends on the accelerator, CPU, memory configuration, and software |
| Z-NAND/Z-SSD | A specialized, low-latency enterprise-flash tier positioned historically between DRAM and conventional NVMe storage | Current product availability, supported firmware and drivers, latency under your queue depth, endurance, and platform qualification | Much of the concrete evidence is historical and vendor-authored; old comparisons must not be treated as current benchmarks |
| NVMe SSD | Persistent model, dataset, checkpoint, and cache storage; selected offload designs | Capacity, sustained throughput, random-read IOPS, tail latency, endurance, power, cooling, and form factor | End-to-end latency includes the controller, host, software, filesystem, and data path; a drive specification alone does not predict token latency |
| zNAND-O | A developing NAND direction that Samsung describes for edge-AI use | Whether a supported product exists for your platform and whether independent workload data is available | Samsung describes it as a concept with versions in development, not as a generally available retail device |
NVIDIA’s technical blog, dated January 25, 2023, describes the AI storage hierarchy as “storage devices, a data fabric, and GPU memory, with performance and latency improving at each higher level.” That is vendor guidance rather than a standards definition, but it captures the design principle: capacity grows as data moves away from the accelerator, while the cost of each access usually rises.
When DRAM or accelerator memory should be your priority
Fit the hot working set first
Calculate the memory required by model weights in their runtime representation, temporary activations, the KV cache, framework overhead, and the maximum concurrent requests. Include headroom for allocator fragmentation and software updates. If that working set does not fit, an SSD upgrade cannot fix the fundamental placement problem; you must change the model, quantization, batch or context policy, accelerator, or offload strategy.
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Distinguish accelerator memory from generic DRAM
High-bandwidth memory integrated into an accelerator is part of that platform, not a normal retail DIMM upgrade. Host DRAM can stage data and serve CPU-side indexes, but transfers across the host-to-accelerator link add a separate cost. Samsung’s 2026 HBM4 material reports up to 3,300 GB/s for HBM4; that figure describes HBM4, not ordinary DRAM or an NVMe SSD, and should be used only as context for why active tensors belong close to the accelerator.
Use DRAM as a cache deliberately
Host DRAM can cache frequently accessed retrieval records, metadata, and model shards. Define an eviction policy and observe hit rate, memory pressure, and the latency of misses. A larger DRAM pool may deliver more consistent latency than a faster SSD if the workload repeatedly revisits the same data.
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Where NVMe SSDs fit
Persistent capacity for servers and workstations
NVMe is the practical default for local model files, checkpoints, datasets, and logs. For a workstation, a consumer NVMe drive can provide that persistent tier, but it is not equivalent to a data-center enterprise SSD in endurance, power-loss protection, firmware behavior, cooling requirements, or qualification. For an inference server, evaluate enterprise drives designed for sustained, concurrent workloads.
PCIe generation is not an application result
A newer PCIe link can increase potential bandwidth, yet application performance still depends on queue depth, request size, controller parallelism, CPU overhead, filesystem behavior, decompression, encryption, and the transfer into accelerator memory. A sequential specification may describe a large model read while saying little about many small retrieval reads or tail latency during concurrent inference.
Offload only with a measured software path
Some serving stacks can page selected weights, KV-cache blocks, or retrieval data to NVMe. The design is worthwhile only when the resulting throughput and tail latency meet the service target. Test page faults, prefetch accuracy, batching, queue depth, and whether storage traffic competes with checkpoint writes or telemetry. If every token waits on a storage miss, extra SSD capacity can make the system cheaper but not responsive.
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What “Z-NAND” means in practice
Historical Z-SSD positioning
Samsung’s Z-NAND brief and SZ985 Z-SSD brochure from 2017–2018 positioned specialized flash as a low-latency tier between DRAM and conventional NVMe SSDs. Those documents explain the intended role: reduce flash access latency for demanding enterprise workloads without treating flash as volatile working memory.
The age and provenance of that evidence matter. The published comparisons are historical, vendor-authored results, and the older product’s figures are not a contemporary baseline for every current SSD. Before selecting a Z-NAND or Z-SSD device, verify that the exact model can still be purchased, that firmware and drivers support the host, and that your application has measurements at the required queue depth and concurrency.
Questions to ask before considering a specialized flash tier
- Is the workload limited by storage latency, or is the real bottleneck CPU preprocessing, PCIe transfer, accelerator memory, or software scheduling?
- Does the serving framework support the device and its desired access mode, including direct I/O or memory-mapped access?
- What are the measured p99 and p99.9 read latencies during concurrent inference, not just an advertised average?
- Does the device provide the endurance, power-loss protection, cooling, form factor, and firmware lifecycle required by the deployment?
- Would additional DRAM or a larger accelerator memory pool keep the hot set resident more cheaply and predictably?
What zNAND-O is—and is not
Samsung introduced zNAND-O in 2026 material as a next-generation NAND design for edge AI. The company describes a design target of read latency below 3 microseconds and bandwidth of 200–400 GB/s. These are Samsung-reported goals, not independent measurements of a generally available retail SSD.
The same material characterizes zNAND-O as a concept with versions in development. It should therefore be treated as a roadmap direction. Do not build a purchase plan, capacity estimate, or production dependency on those figures until a specific product, interface, qualification list, and independent workload data exist.
A step-by-step selection process
- Map every data class. List model weights, execution buffers, KV cache, retrieval indexes, feature data, checkpoints, logs, and archives. Record whether each item is read sequentially, read randomly, written, or rewritten during serving.
- Define the service target. Set first-token latency, per-token latency, throughput, concurrency, availability, and recovery objectives. Include tail targets such as p95 or p99, because averages can hide queueing during bursts.
- Size accelerator memory and DRAM. Calculate the hot working set for the largest supported model, context, batch, and concurrency. Add operational headroom. If it does not fit, decide what changes before evaluating SSD offload.
- Assign persistent capacity to NVMe. Size for model versions, checkpoints, datasets, temporary files, and free-space requirements. Select endurance, power-loss protection, cooling, and form factor for the actual platform rather than a desktop specification sheet.
- Evaluate specialized flash only for a demonstrated gap. For Z-NAND or another low-latency device, document the current model, availability, software support, and benchmark conditions. A historical product position is not evidence that the same benefit exists in your deployment.
- Validate the complete transfer path. Measure storage-to-host and host-to-accelerator movement, decompression, preprocessing, synchronization, and application scheduling. If your stack supports GPUDirect Storage, test direct transfers between GPU memory and NVMe or NVMe-oF storage; the benefit depends on compatible software and infrastructure.
- Compare total operating cost. Include drive count, spare capacity, endurance replacement, power, cooling, adapters, support contracts, and the engineering cost of operating an offload tier. Compare those costs with more DRAM, a larger accelerator, or a simpler capacity-oriented SSD design.
How to benchmark an inference storage path
Use the real request mix
Run the model and retrieval software that will serve production traffic. Include cold starts, warm starts, concurrent model loads, checkpoint activity, and the expected mix of sequential and random reads. A synthetic sequential benchmark can be useful for capacity planning but cannot establish token latency.
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Record more than peak bandwidth
- Application latency: time to first token, inter-token latency, and end-to-end response time.
- Tail latency: p95, p99, and p99.9 under the intended concurrency and queue depth.
- Throughput: requests or tokens per second while meeting the latency target.
- Storage behavior: read and write bandwidth, IOPS, request size, queue depth, cache hit rate, and throttling.
- System effects: CPU utilization, PCIe link utilization, host-memory pressure, accelerator utilization, thermal throttling, and power draw.
- Failure behavior: recovery after a drive restart, degraded redundancy, a cold cache, or a model reload.
State the test conditions
Document model size and format, batch and context, concurrency, accelerator and host configuration, filesystem and runtime, data-compression settings, drive temperature, firmware, and whether results are vendor claims or independent measurements. Without those conditions, figures such as “microseconds” or “GB/s” cannot be transferred safely to another system.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Reference architectures by deployment type
Single workstation
Put the active model in accelerator memory, use system DRAM for staging and indexes, and use one or more NVMe SSDs for models, datasets, and checkpoints. Prioritize sufficient capacity, sustained behavior, cooling, and backup over a specialized flash tier unless profiling shows storage stalls during the user-visible path. A consumer NVMe SSD is appropriate for local persistent files when its endurance and thermal limits match the workload.
Multi-GPU inference server
Plan placement per accelerator, account for host-to-device topology, and avoid making every GPU contend for one storage queue. Enterprise NVMe devices can provide persistent capacity and parallel model staging. If the software supports direct GPU-to-storage transfers, benchmark that path against DRAM staging; direct I/O is not automatically faster when requests are small or preprocessing remains CPU-bound.
Large-model server with explicit offload
Use DRAM for the most frequently reused offloaded blocks and NVMe for colder blocks. Define prefetch and eviction policies, monitor page-fault or miss rates, and cap concurrency if storage contention causes tail latency to violate the service objective. A lower-latency flash tier can be considered only after this software path is instrumented.
Edge AI appliance
Capacity, power, thermal limits, and physical availability may dominate. zNAND-O’s stated edge-AI direction is not a currently purchasable assumption. Choose an available, supported memory and storage configuration, then validate boot, model update, recovery, and sustained thermal behavior at the target ambient temperature.
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Current examples and how to interpret them
| Example | What is established | How to use the information |
|---|---|---|
| Samsung PM1763 | Samsung announced mass production on July 8, 2026, describing it as a PCIe 6.0 enterprise SSD for AI and HPC servers. Samsung gives an example of transferring a 40 GB large language model in approximately 1.4 seconds. | Use it as an example of a current enterprise storage direction and a vendor example under stated conditions, not as a universal model-load time or an independent benchmark. |
| Samsung PM1753 | Samsung’s 2026 material references it in an inference-storage architecture. General retail availability and a direct performance comparison with PM1763 are not stated. | Verify exact availability, qualification, interface, and workload results before specifying it. |
| Samsung SZ985 Z-SSD | A historical enterprise product documented in 2017–2018 Z-NAND and Z-SSD material. | Use it to understand the historical low-latency-flash concept; do not use its old figures as current SSD baselines. |
| Samsung zNAND-O | A next-generation NAND design announced in 2026 material for edge AI, with versions described as in development. | Treat the below-3-microsecond latency and 200–400 GB/s bandwidth figures as Samsung design targets, not proof of a shipping product. |
Common mistakes and corrective actions
“The fastest SSD will replace more DRAM.”
Why it fails: SSD access is persistent block I/O with controller, software, and transfer overhead. Correction: keep repeatedly accessed execution state in accelerator memory or DRAM; use SSD for capacity and only measured offload.
“Peak sequential bandwidth predicts generation speed.”
Why it fails: generation may issue small, concurrent reads or no storage reads once weights are resident. Correction: benchmark first-token and inter-token latency with the real request pattern.
“A historical Z-SSD comparison is a current buying guide.”
Why it fails: the SZ985 evidence is from 2017–2018 and compares products available at that time. Correction: verify a current device, support status, and independent measurements under your workload.
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Why it fails: zNAND-O is described as a concept in development. Correction: record it as a future technology direction and select an available, qualified component for production.
“Direct GPU storage always improves inference.”
Why it fails: GPUDirect Storage requires compatible hardware and software, and the workload may be limited elsewhere. Correction: compare direct transfers with DRAM staging while measuring CPU use, synchronization, queueing, and tail latency.
A practical decision matrix
| Situation | First choice | Next investigation |
|---|---|---|
| Weights and cache fit in accelerator memory | Accelerator memory for hot state; NVMe for persistent files | Optimize model loading and checkpoint handling rather than buying specialized flash |
| Weights fit in DRAM but not accelerator memory | Increase accelerator capacity or redesign placement; use DRAM for staged data | Measure host-to-device transfers and concurrency effects |
| Large model must be loaded or swapped frequently | Enterprise NVMe sized for sustained reads and parallelism | Test prefetch, sharding, direct storage transfers, and startup latency |
| Random retrieval reads cause tail-latency spikes | More DRAM caching and an NVMe device qualified for random concurrent reads | Measure cache hit rate, queue depth, p99 latency, and index layout |
| A documented storage miss remains the bottleneck after software tuning | Consider a specialized low-latency flash product if currently available | Confirm support, endurance, cooling, and independent workload results |
| Considering zNAND-O for a new deployment | Use an available supported memory and SSD design instead | Monitor future product announcements; do not assume roadmap availability |
How to make the final choice
Start with the memory required to serve the largest supported request at the promised concurrency. If the hot set fits in accelerator memory and DRAM, buy reliable NVMe capacity for persistence and recovery, then optimize loading and caching. If storage stalls remain after profiling, compare enterprise NVMe devices using application-level tail latency, not a single sequential number. Consider historical Z-NAND products only as a narrowly scoped product-and-support question, and keep zNAND-O in the roadmap category until a specific, qualified device is available.
There is no neutral, apples-to-apples statistic that ranks modern DRAM, Z-NAND, and NVMe SSDs for every inference workload. The winning design is the one that keeps hot data close to the accelerator, supplies enough persistent capacity, and proves its end-to-end latency, throughput, endurance, power, and recovery behavior on the complete platform.
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