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Choose nonvolatile memory from the data’s job, not from a technology name. Firmware that must boot or execute in place, configuration values changed occasionally, high-rate event logs, and bulk files have different requirements for density, latency, endurance, retention, power-fail recovery, software, and cost. Start by describing the workload, shortlist suitable memory families, then verify the exact device datasheet and your complete system lifetime model.
Start by defining what must survive power loss
Separate immutable or rarely changed firmware from mutable application state before comparing parts. A single product may need two memories: NOR for boot images and execute-in-place code, plus F-RAM, EEPROM, nvSRAM, or a managed flash area for frequently updated records.
Classify the data
- Boot and firmware images: Usually require predictable reads, sufficient density, update recovery, and sometimes execute-in-place (XIP), where the processor fetches instructions directly from the memory.
- Configuration and calibration: Usually consists of small records written occasionally. Granularity, page boundaries, write time, endurance, and atomic replacement matter more than maximum density.
- Event logs and counters: Can generate many writes, often concentrated in a small address range. Write distribution, latency, energy per write, and power-fail completion are central.
- Bulk files or captured data: Favors high capacity and low cost per bit. A controller or firmware must normally handle error correction, bad blocks, wear, and recovery.
Record the capacity needed today, expected growth, update size, update frequency, whether accesses are sequential or random, whether writes are concentrated in one location, and whether the last record must be committed after power disappears. Also record the maximum boot time, acceptable write latency, available RAM, supply voltage, temperature range, package limits, and required product life.
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1. Quantify the write profile
Estimate updates per second or day, the number of operating days, years in service, and the percentage of writes hitting each region. Distinguish a logical record update from the physical operations it causes. A one-byte change may trigger a page program, sector erase, garbage-collection move, or duplicated journal record.
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An illustrative workload of 10 updates per day for 10 years produces 36,500 logical updates. That number does not prove a flash device will last: if every update erases the same sector, the physical stress is concentrated; if records are distributed across 100 sectors, it is very different. Include bootloader updates, factory provisioning, diagnostics, and maintenance writes in the same model.
2. Shortlist memory families by workload
| Family | Best starting use | Important strengths | Costs and cautions |
|---|---|---|---|
| NOR flash | Firmware, boot code, random reads, and XIP | Random access and fast reads are suited to code storage and direct execution, as described by Infineon’s NOR flash family information. | Erase and program operations are relatively coarse compared with byte-oriented memories. Small, frequent updates need a data-management scheme, and density, erase time, endurance, and read-while-write behavior vary by part. |
| NAND flash | High-density data and bulk storage | Lower cost per bit and large capacities can make it economical for files, images, and logs. | Organization, error correction, bad-block handling, wear management, retention, and controller requirements must be designed in. The Micron NOR/NAND guide is a useful orientation, but exact ratings must come from the selected device. |
| Serial EEPROM | Small persistent settings and occasional updates | Simple interfaces and small-write behavior can reduce firmware complexity for modest data sets. | Write granularity, page boundaries, write-cycle time, endurance conditions, voltage range, and capacity differ by device. Microchip warns in AN537 that EEPROM endurance is application-dependent. |
| F-RAM | Frequent capture, low-latency writes, and energy-constrained logging | Infineon lists I2C, SPI, QSPI, and parallel products across multiple densities. Its product-family page claims up to 100 trillion read/write cycles. | Verify the exact density, interface, voltage, package, temperature grade, and price. The 100-trillion figure is a manufacturer family claim, not a universal rating or an independent comparison. |
| nvSRAM | Fast SRAM-like access with nonvolatile capture, especially logging | The Infineon nvSRAM family page describes instant capture on power interruption and lists serial devices from 64 kbit to 1 Mbit and parallel devices from 64 kbit to 16 Mbit. | Check the exact capture mechanism, required hold-up or energy, capture time, voltage behavior, and whether the system can guarantee the specified power-interruption conditions. |
| MCU flash emulation | Modest state storage when a supported MCU has spare flash | Can remove a separate EEPROM and its bus wiring. | Requires reserved pages, wear leveling, garbage collection, interrupted-write recovery, and careful power-fail design. The documented method is family-specific, not a universal MCU feature. |
Should you use NOR or NAND flash?
Use NOR as the initial candidate when the processor needs random instruction or data reads, a boot image must be mapped predictably, or XIP is valuable. Confirm density, address mode, read throughput, program and erase times, sector size, and whether code can execute while another region is being programmed.
Use NAND when capacity and cost per bit dominate and the system can provide the management layer that NAND requires. Raw NAND normally exposes pages, erase blocks, spare areas, bad blocks, and bit errors. Your controller or firmware may need ECC, bad-block tables, wear leveling, logical-to-physical mapping, journaling, and recovery after interrupted operations. Managed NAND moves some of that burden into the device, but its interface, lifetime behavior, and firmware assumptions still need verification.
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When EEPROM, F-RAM, or nvSRAM is a better fit
EEPROM for small, understandable records
EEPROM is attractive when the data set is small and updates are infrequent enough that a straightforward write protocol meets the lifetime target. Check whether the device supports the write size you need or silently rewrites an entire page. Keep records within page boundaries unless the datasheet specifies crossing behavior. Measure or budget the write-cycle time, and define what the firmware does if reset occurs while the internal write is busy.
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Microchip’s endurance guidance emphasizes that a headline cycle count is not a complete life guarantee. Endurance depends on the application’s write pattern and conditions, so obtain the exact test conditions and apply your own distribution, temperature, and mission profile.
F-RAM for high-frequency, low-energy writes
F-RAM can simplify logging because writes are typically fast and do not require a flash-style erase cycle. Infineon claims that its F-RAM chips consume 200 times less energy than EEPROM and 3,000 times less than NOR flash on its product page. Those are vendor comparisons under the manufacturer’s stated conditions; they are not universal values. Verify that the particular part, bus speed, voltage, and transaction size match your design.
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nvSRAM for volatile-speed operation with capture
nvSRAM presents an SRAM-like interface while retaining data through a nonvolatile capture operation. It can be useful when a logger needs very low access latency and can tolerate the device-specific capture procedure. Confirm whether capture is automatic or commanded, the required supply-hold-up profile, how status is reported, and how the firmware validates data after restart. The family capacities listed by Infineon are a product-range description; select an exact part and read its datasheet.
Can MCU flash replace EEPROM?
Sometimes. On-chip flash can emulate EEPROM for modest state storage when the microcontroller has suitable spare pages and a proven algorithm. It is not equivalent to a byte-write EEPROM: flash generally programs in larger units and must erase pages or sectors, so the software must spread wear and recover from interrupted operations.
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ST AN4894, revision 12 (July 2026), documents an STM32 solution that uses at least two pages, wear leveling, background page erase, and robustness features for asynchronous reset and power failure. The method applies to the STM32 families listed in that document. Do not assume the same algorithm, page format, timing, or guarantees apply to another MCU vendor or to an unlisted STM32 family.
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What an emulation implementation must provide
- Reserve enough pages for active data, a transfer area, metadata, and growth. Calculate capacity after headers, validity markers, alignment, and obsolete records are included.
- Use a wear-leveling policy that matches the real write distribution. A rotating page scheme is not useful if one counter or index remains fixed in one location.
- Define an atomic record format with sequence number, length, payload, and integrity check. A new record must become valid only after its complete contents are safely programmed.
- Handle reset during programming, page transfer, erase, and metadata update. Startup recovery must identify the newest complete record and discard partial data.
- Budget background erase time, interrupt behavior, RAM usage, and the possibility that the MCU cannot execute from a page while it is being erased or programmed.
How much write endurance do you need?
Calculate a required physical endurance, not just a logical update count. Start with:
required physical cycles per location = logical updates × physical operations per update ÷ effective wear distribution
Then add a margin for manufacturing tests, field service, retries, corrupted transfers, firmware updates, and worst-case temperature. For flash, include the erase-block size and garbage-collection moves. For emulation, include page cleanup and migration. For EEPROM, include the device’s write granularity and any page rewrite caused by a partial update.
Retention and endurance interact. A memory heavily cycled near its endurance limit may have different retention behavior than a lightly used part, and elevated temperature can reduce margins. Check the exact datasheet’s retention conditions at the expected storage and operating temperatures, not a typical value from another density or family.
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Microchip summarizes the reliability problem in its TB072 application-note description dated June 24, 2015: "Endurance, data retention, temperature, operating voltage and frequency, and programming time all play significant roles in the reliability of the device." Use that as a design checklist, then replace generic assumptions with current, part-specific specifications from TB072 and the selected component datasheet.
Design for power failure and data integrity
Decide what must be true if power fails during every nonvolatile operation. A last-gasp record may need enough hold-up energy to finish a page program, capture, or metadata update. If the energy budget cannot guarantee completion, use a transactional format that can safely resume or roll back.
A robust update pattern
- Write the new payload to an unused slot or page.
- Write a sequence number and integrity value, such as a CRC, after the payload has been verified in RAM.
- Commit a validity marker only after all required bytes are programmed successfully.
- On boot, scan for the newest valid sequence and ignore records without a complete marker or valid integrity check.
- Reclaim old pages only when the active record is safely represented elsewhere; make page transfer restartable after reset.
For nvSRAM or other capture memories, follow the device’s specified power-interruption sequence rather than assuming that any falling supply will trigger a reliable save. For flash and EEPROM, check whether reads are allowed during programming, whether brownout reset timing can interrupt the operation, and whether the reset circuit provides the voltage and time stated in the datasheet.
Compare exact devices, not technology labels
| Check | Questions to answer before design-in |
|---|---|
| Capacity and growth | Does usable capacity include metadata, redundancy, bad-block reserve, wear-leveling space, and future firmware or log growth? |
| Interface | Does the MCU or SoC support the bus, address width, clock rate, timing modes, and required boot configuration? |
| Voltage and signal integrity | Are supply and I/O levels compatible across startup, brownout, and power sequencing? Are level shifters, pull-ups, or termination required? |
| Granularity and latency | What are the minimum program and erase units, page boundaries, busy times, read latency, and read-while-write restrictions? |
| Endurance and retention | At what temperature, voltage, data pattern, and operation mix are the ratings specified? Do they cover the mission profile and service life? |
| Power failure | What happens during interrupted writes, erase, page transfer, or nonvolatile capture? Is hold-up capacitance or a supervisor required? |
| Software burden | Will the design need ECC, bad-block management, wear leveling, journaling, a translation layer, bootloader changes, or a vendor library? |
| Mechanical and qualification | Does the package fit the board, assembly process, vibration profile, and required automotive, industrial, or other qualification? |
| Lifecycle and sourcing | Is the part available for the product’s planned life, with a second source or migration path? Confirm current status at design-in; a family longevity statement does not guarantee every ordering code. |
| Total system cost | Include controller silicon, PCB area, power components, firmware development, validation, test time, field failures, and replacement risk—not only the memory’s unit price. |
Temperature, qualification, and lifecycle decisions
Specify operating and storage temperatures separately. Retention claims often assume a stated temperature and a defined number of program or erase cycles; they should not be extrapolated to a hotter enclosure or a different duty cycle. If the product experiences thermal cycling, vibration, radiation, or long unpowered storage, request the qualification data that covers those conditions.
Availability is also a technical constraint. Infineon describes a longevity program for its NOR family, but that does not establish availability for every device, package, density, or region. Check lifecycle notices, minimum order quantities, lead times, approved alternates, and whether an alternate has compatible command sets and boot behavior.
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Worked choices for common embedded designs
Bootable industrial controller
Start with NOR sized for the bootloader, redundant firmware images, recovery metadata, and growth. Confirm XIP or copy-to-RAM requirements, sector erase time, read-while-write behavior, and a bootloader scheme that never destroys the last known-good image. Store counters and configuration separately unless the NOR data layer has demonstrable wear leveling and power-fail recovery.
Battery-powered sensor with frequent samples
Calculate samples per wake cycle, retention time, energy available for a write, and the percentage of samples that must survive an abrupt shutdown. Compare F-RAM, nvSRAM, and a carefully managed flash design using measured energy and latency for the exact transaction size. A family-level energy claim is only a screening input; verify the selected part under the battery’s voltage range and bus speed.
Gateway storing large files
Shortlist NAND or a managed high-density device when capacity and cost per bit dominate. Design ECC, bad-block handling, wear leveling, filesystem or translation-layer recovery, and safe update sequencing before selecting the package. If the processor requires direct instruction fetch, keep boot code in a memory optimized for random reads rather than forcing bulk-storage media into that role.
Small appliance with a few settings
A serial EEPROM may be the simplest solution if update frequency, page size, write time, and endurance meet the calculated requirement. MCU flash emulation can reduce the bill of materials when the MCU is explicitly supported and enough flash is reserved for wear leveling and recovery; include the engineering and validation cost in the comparison.
A decision checklist
- Have firmware, configuration, logs, and bulk data been separated by workload?
- Are capacity, growth, update size, update rate, access pattern, and write concentration documented?
- Has logical activity been converted into physical program, erase, capture, and cleanup operations?
- Are endurance and retention checked at the actual temperature, voltage, and mission profile?
- Is the power-fail sequence proven for interrupted writes and page transfers?
- Are ECC, bad blocks, wear leveling, journaling, and recovery owned by a defined hardware or software component?
- Have package, bus timing, signal levels, qualification, lifecycle, second sourcing, and total system cost been compared for exact ordering codes?
- Has the design been tested with brownouts, repeated resets, maximum temperature, full memory, and worst-case write distribution?
Bottom line
There is no universally best nonvolatile memory. NOR is usually the first place to look for boot code and random reads; NAND is a candidate for managed, high-density storage; EEPROM fits small, occasional updates; F-RAM and nvSRAM deserve attention when writes are frequent or latency and energy are critical; and MCU flash emulation can work when its algorithm and MCU scope are explicit. The correct choice is the exact device and data-management design that meet your workload, lifetime, power-fail, environmental, interface, software, availability, and total-cost requirements together.
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