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Benchmark single-qubit gate speed and fidelity as two related but separate measurements. Read the calibrated single-qubit gate duration for a specific native operation, then measure its operational error with single-qubit randomized benchmarking (RB). A useful result reports nanoseconds per gate, error per Clifford (EPC) or error per gate (EPG), T1 and T2 coherence, readout error, calibration state, compilation details, timestamps, and uncertainty. Without that context, a fast-looking gate or a low error number cannot be compared fairly with another qubit, calibration cycle, or processor generation.
What this benchmark actually measures
A quantum processor does not have one universal “gate speed” or “gate fidelity.” Each qubit, native instruction, pulse schedule, compiler version, and calibration can change the result. Start by choosing one operation on one qubit—for example, X, SX (square-root of X), or RX—and define exactly what is being compared.
- Speed is the calibrated duration of the finite-duration operation, normally reported in nanoseconds per gate.
- Operational fidelity is inferred from how reliably the processor preserves a prepared state through a sequence of gates. Standard RB usually reports an average error per Clifford; conversion can produce an error per primitive gate.
- Coherence headroom comes from T1 and T2, which indicate how much relaxation and dephasing can occur during the gate.
- Measurement contribution is represented by readout error and should not be mixed into the gate-error number.
- Stability is the repeatability of those values across timestamps, recalibrations, and experimental conditions.
A virtual RZ rotation is a special case. It is implemented as a software frame update rather than a driven pulse, so a provider may report zero duration and zero reported error for it. Do not compare that software operation with a finite-duration X or SX pulse as though they were equivalent physical actions.
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Fix the operation and qubit
Record the qubit identifier and the exact native instruction. “Single-qubit fidelity” is incomplete unless it says which gate was benchmarked. If the processor exposes ID, SX, X, and RX properties, keep the operation label exactly as the backend reports it. An RX gate may also require an angle; record that angle and whether the compiler decomposed it into another basis.
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Fix scheduling and spectator conditions
State whether the gate ran in isolation or while neighboring qubits were active. Simultaneous spectators can create crosstalk that is invisible in an isolated experiment. Also record direction where the hardware or pulse schedule makes direction meaningful, inter-gate delays, reset behavior, and whether measurement and reset were included in the timing window.
Preserve the software and calibration context
Save the backend name and revision, compiler or transpiler version, pulse or instruction definition, calibration timestamp, and experiment start and end times. IBM describes daily benchmarking that produces T1, T2, measurement-fidelity, and gate-error metrics; those values can drift with calibration timing and experimental conditions. A result without a timestamp is therefore not a durable device specification.
| Comparison axis | What to record | Why it matters |
|---|---|---|
| Duration | Calibrated nanoseconds for the selected finite-duration native gate | Separates physical pulse time from software or scheduling overhead |
| Operational fidelity | RB-derived EPC or EPG, with the convention and uncertainty | Shows average computational performance under the chosen protocol |
| Coherence headroom | T1 and T2, plus their measurement timestamps | Indicates relaxation and dephasing exposure during the gate |
| Measurement contribution | Readout error or measurement fidelity reported separately | Prevents readout faults from being misidentified as gate faults |
| Stability | Repeated values across calibration cycles and defined intervals | Reveals drift and recalibration sensitivity |
| Execution context | Compiler, pulse schedule, waits, spectators, and shot settings | Makes results reproducible and comparable |
Measure single-qubit gate duration
Use the backend’s calibrated duration for the exact instruction under test. IBM’s QPU information guide exposes gate-length and randomized-benchmarking error fields for ID, SX, X, and RX operations. Copy the duration in nanoseconds rather than inferring it from a circuit diagram: a diagram’s gate symbol does not reveal pulse width, alignment constraints, or inserted waits.
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Report the speed number correctly
The primary speed metric is nanoseconds per gate. You may also show the reciprocal idealized rate:
idealized gates per second = 1 / (duration in seconds)
For example, a duration written as d nanoseconds corresponds to 10^9 / d idealized gates per second. This reciprocal is a pulse-rate calculation, not a claim about application throughput.
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Explicitly state what the duration excludes. A pulse-duration result normally excludes queueing, readout, reset, classical processing, and any inter-gate waits. If your question is how quickly a complete workload finishes, measure circuit-layer time or wall-clock throughput separately and include those overheads. Never present pulse duration alone as end-to-end processor speed.
Run standard single-qubit randomized benchmarking
Randomized benchmarking estimates average operational error while reducing sensitivity to state-preparation and measurement (SPAM) errors. The standard one-qubit experiment prepares a reference state, applies random Clifford operations, appends a mathematically compensating inverse Clifford, and measures whether the reference state survived.
Choose a controlled sequence design
Select a sequence-length grid, such as several increasing values of m, and a fixed number of independent randomizations at each length. The exact grid and counts are part of the benchmark definition. Use the same lengths, randomization count, shots per sequence, inverse-generation method, and fit procedure for every qubit or device in the comparison.
- Prepare the reference state. Usually initialize the computational-basis state used by the backend’s standard protocol. Record reset and initialization assumptions.
- Generate random Clifford sequences. For each selected length
m, draw many random one-qubit Clifford strings using the same sampling method across all comparisons. - Append the inverse Clifford. Compute the single Clifford that ideally returns the accumulated sequence to the starting state. The inverse is part of the experiment, not an optional cleanup gate.
- Compile consistently. Decompose the Clifford operations into the processor’s native basis with the same compiler or transpiler settings. Save the resulting instruction stream, because the number of primitive pulses per Clifford affects EPG conversion.
- Execute many shots. Run enough repetitions to estimate the survival probability at every length and randomization. Keep shot count fixed when comparing conditions.
- Measure in the computational basis. Define survival as the probability of observing the expected reference outcome. Keep readout calibration separate from the RB fit.
- Average by sequence length. Average survival across randomizations at each
m; retain the spread so the fit uncertainty reflects finite sampling and sequence-to-sequence variation. - Fit the decay. Fit survival to an exponential-with-offset model such as
A p^m + B, wherepis the decay parameter andAandBabsorb preparation and measurement offsets.
Inspect the fit rather than trusting one number
Plot survival probability against sequence length and show the fitted curve and uncertainty. Check for non-monotonic behavior, poor residuals, or a late-time floor that the model cannot describe. Such features can indicate leakage, drift, insufficient randomizations, or a mismatch between the assumed Markovian decay and the device behavior. Report the sequence grid, randomization count, shots, fit model, parameter uncertainty, and any data excluded with a reason.
Convert the RB decay into a labeled fidelity metric
For a one-qubit depolarizing interpretation, average gate fidelity is one minus average gate error. The important qualification is what “gate” means. Standard RB most directly produces an error per Clifford (EPC), because each sequence step is a Clifford operation. If you want the error of a primitive X, SX, or RX pulse, report an error per gate (EPG) and state the conversion convention.
Keep EPC and EPG distinct
A Clifford generally compiles into a variable number of primitive basis gates. Dividing EPC by an average primitive count is only an approximation unless the conversion model accounts for the basis and error assumptions. IBM documents explicit EPC/EPG conversion helpers for one-qubit basis gates; use the helper or formula appropriate to the dimension and basis, and record which convention was applied.
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Do not write “fidelity 99.9%” without naming the metric. A complete label looks like “RB error per Clifford,” “converted SX error per gate,” or “average gate fidelity inferred from the one-qubit depolarizing model,” followed by uncertainty and timestamp. If the provider reports a gate-error field directly, preserve whether it is an RB-derived value, a per-Clifford value, or a per-primitive value.
Understand the historical NIST figure
A trapped-ion randomized-benchmarking demonstration hosted by the National Institute of Standards and Technology reported a one-qubit error probability of 0.00482(17) per randomized pi/2 pulse. The parenthetical notation expresses the reported uncertainty. This is a 2007 historical result, not a universal present-day target and not a direct prediction for another processor technology.
Isolate a particular gate with interleaved randomized benchmarking
Standard RB averages the implemented Clifford set. If the question is specifically “How good is this X or SX gate?”, use interleaved randomized benchmarking (IRB). Construct a reference RB experiment and a second experiment in which the target gate is inserted between the random Clifford operations. Compare the two fitted decay parameters under otherwise identical conditions.
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Relate gate error to T1, T2, and readout error
Use coherence as a diagnostic, not a substitute for RB
Compare the measured RB error with a coherence-limit estimate derived from the gate duration and the measured T1 and T2. A short gate leaves less time for relaxation and dephasing, but it can still have poor fidelity because of control-amplitude error, calibration mismatch, leakage, or crosstalk. Conversely, a longer pulse can be accurate if its control errors are lower. T1 and T2 therefore provide explanatory context rather than a replacement for an operational benchmark.
Keep readout error separate
Readout error affects the observed survival probability and can obscure a gate problem. Record the backend’s readout error or measurement fidelity at the same calibration state, but do not add it to the gate-error field or subtract it informally from EPC. The RB offset parameters absorb some SPAM effects; they do not turn readout into a measured gate property.
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Test drift and recalibration effects
Repeat the benchmark after a defined interval, after recalibration, and after meaningful compiler or pulse changes. Preserve start and end timestamps for every run. Compare the full distribution, not only the best value: median, spread, and outliers reveal whether a gate is consistently usable or merely excellent at one calibration moment.
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RB is an average operational metric. It can hide gate-dependent errors, coherent over-rotations, time-correlated noise, leakage outside the computational subspace, and crosstalk from simultaneous operations. A low EPC does not prove that every Clifford or every circuit layer behaves equally well.
Use gate-set tomography (GST) when you need a detailed, predictive model of the complete implemented gate set. GST can expose gate-dependent and coherent effects that an averaged RB decay compresses into one parameter. IBM Research describes GST as a detailed, predictive characterization method for processor logic operations. For multi-qubit workloads, add cycle-level or layer-level tests that activate the spectators and scheduling patterns used by the application.
Compare processors and qubits with a common reporting table
The following layout keeps unlike quantities from being conflated. Populate every row from the same experiment definition and calibration window; if a provider does not state a value, write “not stated” with the source and date rather than inferring it.
| Field | Qubit A | Qubit B | Processor or run notes |
|---|---|---|---|
| Native gate and angle | Record exact instruction | Record exact instruction | Do not mix virtual RZ with driven pulses |
| Single-qubit gate duration | Nanoseconds, calibrated | Nanoseconds, calibrated | State whether waits and scheduling are excluded |
| RB result | EPC or EPG with uncertainty | EPC or EPG with uncertainty | Include fit model and sequence settings |
| T1 and T2 coherence | Values and timestamps | Values and timestamps | Use as coherence context |
| Readout error | Separate measurement metric | Separate measurement metric | Do not fold into gate error |
| Simultaneous spectators | Inactive or specified activity | Inactive or specified activity | Controls crosstalk exposure |
| Calibration and software | Backend revision, compiler, timestamp | Backend revision, compiler, timestamp | Required for reproducibility |
Common failure modes and how to correct them
Calling a pulse rate “processor speed”
Symptom: A report converts nanoseconds to gates per second and presents that as application throughput.
Correction: Label it idealized pulse throughput and separately measure circuit-layer or wall-clock throughput with readout, reset, waits, queueing, and classical processing included.
Comparing virtual RZ with X or SX
Symptom: A zero-duration, zero-reported-error RZ appears to dominate a driven gate.
Correction: Explain that RZ is a software frame operation and compare only operations with equivalent physical meaning.
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Reporting EPC as though it were X-gate error
Symptom: “The X error is 0.2%” is derived directly from a Clifford RB fit.
Correction: Call the measured quantity EPC, then provide a documented EPG conversion if the basis, dimension, and assumptions support it.
Ignoring compiler changes
Symptom: Two runs use different decompositions or pulse schedules but are treated as the same experiment.
Correction: Freeze compiler settings, save the compiled instruction stream, and report the primitive-gate composition.
Using one calibration snapshot as a permanent specification
Symptom: A gate value is quoted without a date.
Correction: Include calibration and run timestamps, then repeat after recalibration or other meaningful device changes.
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Over-interpreting a low average error
Symptom: A favorable EPC is used to claim absence of leakage, coherent error, or crosstalk.
Correction: Add IRB, simultaneous-operation tests, GST, or cycle-level methods that target the suspected effect.
Publication-ready reporting checklist
- Identify the processor, backend revision, qubit ID, native gate, and any RX angle.
- Give the calibrated single-qubit gate duration in nanoseconds and define excluded overheads.
- State whether operation was isolated or simultaneous with spectator activity.
- Record pulse or instruction definitions, compiler/transpiler version, and decomposition.
- Describe state preparation, sequence-length grid, randomization count, inverse construction, and shots.
- Show survival data, the
A p^m + Bfit, residuals, and parameter uncertainty. - Label the result as error per Clifford or error per gate; explain every conversion.
- Report T1 and T2 coherence and readout error separately, with matching timestamps.
- Give experiment start/end times and calibration state; repeat to quantify drift.
- Explain whether the result is standard RB, interleaved RB, GST, or another method.
- List limitations involving SPAM, leakage, coherent errors, time correlation, and crosstalk.
Interpreting the final result
The most defensible conclusion is multidimensional: one gate may be faster but less accurate, while another may be slower yet have greater coherence headroom or better stability. Choose according to the workload and report both axes. For processor comparisons, prefer a matched protocol over headline numbers: same sequence design, same shot and randomization budgets, equivalent compilation assumptions, equivalent spectator activity, and calibration timestamps close enough to make the conditions meaningful.
A complete benchmark therefore reads like: a specified native gate on a specified qubit took a stated number of calibrated nanoseconds; standard or interleaved RB produced a clearly labeled EPC or EPG with uncertainty; T1, T2, readout error, compiler, pulse schedule, calibration state, and timestamps explain the context; and follow-up tests establish whether the average hides leakage, crosstalk, or drift.
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