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A switched-capacitor filter uses clocked switches and capacitors to move small packets of charge. Averaged over many clock cycles, that transfer behaves like current through a resistor, with an ideal equivalent resistance of Req = 1/(C × fCLK). In a common first-order low-pass topology, this makes the cutoff frequency proportional to the clock frequency: f3dB = (C1 × fCLK)/(2πC2). The analogy is useful, but not complete: the circuit samples its input, so aliasing and clock-related noise or ripple may affect a design.
What a switched-capacitor filter does
A switched-capacitor filter processes a signal by repeatedly connecting capacitors to different circuit nodes under control of a clock. Instead of relying only on a physical resistor to set a time constant, it uses the amount of charge moved per cycle and how often that transfer occurs. This gives designers a way to set or tune a filter’s behavior by changing the clock frequency while leaving capacitor values fixed.
The filter is not simply a conventional continuous-time RC network with a resistor hidden inside it. Its switches operate in clocked phases, and its input and output are subject to sampled-data effects. The resistor analogy describes the average charge flow; it does not mean current flows in exactly the same smooth way as through a real resistor at every instant.
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How charge transfer creates an equivalent resistance
One clock cycle moves a charge packet
In a typical switched-capacitor arrangement, a capacitor called the flying capacitor is connected to one node during one clock phase, then switched to another node during the next phase. In the first phase it acquires a voltage; in the next it transfers charge in response to the voltage difference between the relevant nodes. The phases are non-overlapping, meaning they are timed so the switch connections do not overlap in a way that would connect the nodes together through the switching network.
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For a capacitance C experiencing a voltage difference ΔV, the charge moved in a transfer is approximately:
ΔQ = C × ΔV
Charge is transferred in packets rather than as a perfectly steady stream. If the circuit transfers approximately the same packet once per clock cycle and the clock frequency is fCLK, then the average current is:
I = ΔQ × fCLK
Substituting the charge equation gives an average current proportional to capacitance, voltage difference, and clock frequency. This is the basis of the resistor-like behavior: for a given voltage difference, a higher clock frequency transfers more charge each second and therefore produces more average current.
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The equivalent-resistance model
For the idealized switched-capacitor resistance, the relationship is:
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Req = 1/(C × fCLK)
The units check: capacitance multiplied by frequency has units of farads per second, equivalent to inverse ohms, so its reciprocal is in ohms. Increasing either the capacitor value or clock frequency lowers the modeled resistance. Lowering the clock raises it.
This is an averaged model. The physical current is pulsed as switches connect and disconnect the capacitor, while the equation represents the net effect over clock cycles. Use it to understand the time constant and cutoff behavior of an appropriate topology, not as proof that every switched-capacitor circuit behaves exactly like a continuous resistor under all signal conditions.
How the clock sets cutoff frequency
First-order low-pass example
Consider a first-order low-pass filter in which a switched capacitor C1 replaces a resistor and an output capacitor C2 provides the filtering. For the corresponding RC low-pass, the 3 dB cutoff frequency is:
f3dB = 1/(2πReqC2)
Replacing Req with 1/(C1fCLK) gives:
f3dB = (C1 × fCLK)/(2πC2)
This equation applies to the stated first-order topology. It shows two independent ways to affect the ideal cutoff: increase the clock frequency, or increase the ratio of C1 to C2. If both capacitor values stay fixed, doubling the clock doubles the modeled cutoff. If the clock stays fixed, doubling C1 relative to C2 also doubles it.
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The equation is not a universal formula for every switched-capacitor filter IC. Multi-pole integrated filters have internal architectures that establish their own clock-to-cutoff ratios and response characteristics. For those parts, use the manufacturer’s specified ratio and operating limits rather than assuming the first-order formula describes the whole device.
Manufacturer examples: TLC04 and TLC14
Texas Instruments specifies a nominal 50:1 clock-to-cutoff ratio for the fourth-order Butterworth TLC04 and a nominal 100:1 ratio for the TLC14. The stated ratio error is below ±0.8% for the TLC04 and below ±1% for the TLC14. These specifications describe those devices, not switched-capacitor filters generally.
| Device or example | Clock-to-cutoff relationship | Published qualification |
|---|---|---|
| TLC04 | Nominally 50:1 | Texas Instruments product information lists ratio error below ±0.8% and a cutoff range of 0.1 Hz to 30 kHz. |
| TLC14 | Nominally 100:1 | Texas Instruments product information lists ratio error below ±1%. |
| TLC04 worked example | 64 kHz clock ÷ 50 = 1.28 kHz corner | Texas Instruments’ 2022 example; it illustrates the TLC04 ratio, not a general design rule for all ICs. |
The ratio notation means the clock frequency is a fixed multiple of the cutoff for the specified device. In the TLC04 example, a 64 kHz clock corresponds to a nominal 1.28 kHz corner. The part’s specified ratio error qualifies that relationship; it should not be confused with an accuracy guarantee for an entire application, where other component tolerances, clock behavior, and signal conditions may also matter.
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With a conventional RC filter, changing cutoff commonly means changing a resistor or capacitor value. A switched-capacitor design can instead change the clock and thereby change the effective resistance. This can simplify electronic tuning or allow a filter corner to track a system setting without mechanically or manually changing external RC components.
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Integrated capacitor matching can also improve repeatability compared with relying on absolute resistor values. That advantage is about matching and the device’s implemented relationship; it does not establish that every switched-capacitor part is more accurate than every discrete RC design. The relevant comparison depends on the actual device, target cutoff, tolerance needs, and system behavior.
Clock tuning also introduces a clock into the signal path. A clock that is too high or too low for the signal and selected filter can create problems even if the nominal cutoff equation appears correct. Check the chosen device’s clock limits, input bandwidth, clock-to-cutoff ratio, response and Q, and noise information before treating frequency adjustment as a complete design solution.
Aliasing and the role of an anti-alias filter
A switched-capacitor filter is a sampled-data circuit. Sampling means that input information is observed at clock-related intervals, so signal energy above half the clock frequency can alias into lower frequencies. Once an unwanted component has aliased, the switched-capacitor filter cannot reliably distinguish it from a legitimate in-band component simply by applying its intended low-pass response.
That is why an input RC filter may be needed ahead of the switched-capacitor stage. A passive low-pass can attenuate unwanted high-frequency content before sampling. Whether it is necessary, and how much attenuation it should provide, depends on the signal spectrum and the system: a signal that is already band-limited may need a different approach from one that contains substantial out-of-band energy.
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Do not choose an anti-alias filter solely by looking at the switched-capacitor filter’s advertised cutoff. The relevant question is whether appreciable input energy exists above half the sampling clock frequency and whether that energy could interfere after aliasing. The signal’s bandwidth and spectrum, the clock rate, and the requirements for preserving wanted content determine the answer.
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Ripple and clock feedthrough
Because charge moves in discrete transfers, output transitions can show clock-rate steps or ripple rather than the smooth behavior expected from an ideal continuous-time filter. Switching can also couple clock-related components into the signal path. An output filter may be useful if ripple or switching artifacts fall within a frequency range that matters to the next stage, but the need and suitable filtering depend on the specific part and application.
Charge injection and noise
When an analog switch turns off, charge associated with the switch can be injected into the circuit. Texas Instruments’ application note The Davies Sinusoidal Generator (SBOA550, October 2022) states: “The primary drawback to switched capacitor type filters is the tendency to inject broadband noise into the output due the charge injection of the analog switches involved.” This describes a practical mechanism to consider, not a claim that every filter has the same noise level. Device-specific noise specifications and the application’s bandwidth and dynamic-range requirements matter.
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Clock phase jitter means the switching instants vary slightly in time. In a switched-capacitor filter, that timing variation can contribute noise or distortion. The significance depends on the device and signal conditions; consult the part’s clock requirements and relevant noise or distortion information rather than assuming an ideal, perfectly periodic clock.
Pre-design checklist
- Confirm the part’s supported clock range and clock-to-cutoff relationship.
- Check the specified cutoff range, frequency response, and Q or pole behavior for the intended use.
- Compare the input signal spectrum with half the clock frequency to assess aliasing risk.
- Review noise and switching-artifact information, including charge injection, clock feedthrough, and any stated jitter sensitivity.
- Decide whether input anti-alias attenuation or output ripple filtering is required by the system’s signal and bandwidth.
- For a specific component, verify its current lifecycle, stock, clock specifications, and electrical compatibility before designing around it.
Switched-capacitor versus continuous-time RC filters
Neither approach is universally better. A switched-capacitor filter is attractive when compact implementation, repeatable capacitor matching, or clock-based cutoff adjustment is valuable. A continuous-time RC implementation can be preferable when avoiding sampling artifacts or meeting particular DC-precision needs is more important. Compare the characteristics that affect the actual circuit rather than making the choice from the equivalent-resistance equation alone.
| Design question | Switched-capacitor filter | Continuous-time RC filter |
|---|---|---|
| How is cutoff set or adjusted? | Clock frequency and the part’s capacitor or internal clock-to-cutoff relationship; changing the clock can tune cutoff. | Resistor and capacitor values set the RC time constant; changing cutoff generally involves changing component values. |
| What determines matching or repeatability? | Integrated capacitor matching can improve repeatability compared with relying on absolute resistor values; results remain device-specific. | Depends on the selected resistor and capacitor values and their tolerances; no universal accuracy figure is established here. |
| What sampling concerns apply? | Input energy above half the clock frequency can alias; clock-related ripple, charge injection, and jitter may matter. | It does not rely on the switched-capacitor sampling mechanism described here, so those clock-related artifacts are not inherent in the same way. |
| When might it be a fit? | When compact, accurately clock-tunable filtering is valuable and the sampling and clock behavior are acceptable. | When sampling artifacts or DC precision dominate the decision. |
| What must be checked? | Specific device limits, ratio, input bandwidth, response/Q, noise, and external filtering needs. | Application-specific component values and precision requirements. |
The comparison is qualitative because no universal component count, board-area figure, or accuracy advantage applies across all switched-capacitor and RC implementations. The topology, component selection, and requirements decide those trade-offs.
How to select a clock and cutoff relationship
- Define the signal requirements. Establish the wanted signal bandwidth and the cutoff or response needed from the filter. Also identify whether substantial out-of-band energy could reach the input.
- Choose the circuit model that applies. For the stated first-order topology, use f3dB = (C1fCLK)/(2πC2). For an integrated multi-pole filter, use its manufacturer-specified clock-to-cutoff ratio and response rather than substituting a generic formula.
- Calculate or select the clock. For a device with a known ratio, divide the clock by that ratio to obtain the nominal corner. For the TLC04’s nominal 50:1 ratio, 64 kHz yields 1.28 kHz, as in TI’s 2022 example.
- Check the clock against the signal spectrum. Compare half the clock frequency with the highest meaningful input energy. If out-of-band energy could alias into the wanted band, evaluate input attenuation before the switched-capacitor stage.
- Review non-ideal behavior. Check the device’s clock range, ratio tolerance, response and Q, noise, and clock-related artifacts. Determine whether output ripple or switching components need attenuation.
- Validate device-specific details. Confirm electrical compatibility, lifecycle, and current availability for the selected part rather than assuming a published example is currently purchasable or suitable for every design.
For example, a designer using a TLC04 can start from the documented nominal 50:1 relationship to estimate the clock required for a target corner, then verify the result against the device’s stated range and the application’s sampling and noise requirements. That calculation gives a nominal relationship; it does not replace checking the particular part’s specifications and the complete signal chain.
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