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Spin-transfer-torque magnetoresistive random access memory (STT-MRAM) moved from spintronics research toward commercial memory by solving several different problems in sequence. Spin-transfer torque made current-driven switching practical; CoFeB/MgO magnetic tunnel junctions improved read contrast and efficiency; perpendicular magnetization enabled scaling; and demonstrators, 300 mm process work and foundry integration connected the device to semiconductor manufacturing. The result is a nonvolatile memory used in roles such as SSD write buffering and embedded-memory replacement, although it has not displaced SRAM in the fastest processor caches.
What STT-MRAM is and why it mattered
STT-MRAM stores each bit in a magnetic tunnel junction (MTJ), not as electrical charge in a capacitor or floating gate. An MTJ contains a fixed, or reference, magnetic layer and a free magnetic layer separated by an ultrathin dielectric barrier. The two magnetic layers can point in the same direction (parallel) or opposite directions (antiparallel). Those states have different electrical resistance through tunnel magnetoresistance, so a sense circuit can read one as a 0 and the other as a 1.
The memory is nonvolatile: the magnetic orientation remains when power is removed. That combines data retention with the random access expected of semiconductor memory. The industry challenge was making the magnetic stack switch reliably, read with enough contrast, fit CMOS manufacturing and meet the cost, density, endurance and interface requirements of real products.
How does STT-MRAM work?
- Read the resistance. A small sensing current passes through the MTJ. Parallel and antiparallel magnetization produce distinguishable resistance levels, revealing the stored bit.
- Polarize the write current. During a write, current first passes through the fixed magnetic layer. Its electrons become spin-polarized.
- Transfer angular momentum. When the spin-polarized current enters the free layer, angular-momentum transfer exerts spin-transfer torque on that layer’s magnetization.
- Switch the free layer. A current pulse above the switching threshold reverses the free layer, changing the MTJ from parallel to antiparallel or vice versa. The direction of the pulse determines the target state.
This differs from earlier field-switched MRAM, which generated a magnetic field in current-carrying lines around the cell. As those lines shrink, the current needed to create a sufficient field becomes a density and power problem. STT writing sends current through the junction itself, allowing a smaller write transistor and making denser cells possible in principle.
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What is spin-transfer torque?
Spin-transfer torque is the device-level effect that turns electron spin into a switching force. A ferromagnet filters the current according to spin. When the resulting spin-polarized electrons encounter a second magnetic layer whose orientation differs from theirs, conservation of angular momentum applies a torque to that layer. If the pulse has enough amplitude and duration, the free layer’s magnetization changes direction.
IBM Research credits John Slonczewski’s IBM work in 1996 with identifying spin-transfer-torque switching. That discovery supplied a mechanism, but not yet a manufacturable memory. The subsequent work focused on increasing tunnel magnetoresistance, lowering switching current, controlling thermal stability and integrating the stack with conventional silicon circuits.
The research-to-industry timeline
| Year | Milestone | Why it mattered |
|---|---|---|
| 1996 | John Slonczewski’s IBM work identified spin-transfer-torque switching. | Provided a current-driven way to reverse a magnetic bit. |
| 2004 | IBM and AIST reported high magnetoresistance using MgO tunnel barriers. | Improved the read signal and made MTJs more useful for memory. |
| 2010 | IBM and Tohoku University published development of perpendicularly magnetized STT-MRAM. | Perpendicular magnetic anisotropy supported smaller junctions and higher density. |
| 2013 | IBM and TDK demonstrated product-level yields in an 8 Mb STT-MRAM device. | Showed that the technology could move beyond isolated laboratory cells. |
| Around 2015 | imec places the first STT-MRAM-based products on the market. | Early products served as nonvolatile DRAM and SSD buffers; later designs targeted embedded-Flash replacement. |
| 2017 onward | Everspin’s fiscal-year 2019 filing says STT-MRAM production began in 2017. | The company reported 256 Mb and 1 Gb devices shipping by the time of that filing. |
The dates describe different milestones. “Around 2015” is imec’s broad account of initial products; 2017 is a company-specific production disclosure. Neither should be presented as a single universal launch date for the entire industry.
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Why CoFeB and MgO were a materials breakthrough
In an STT-MRAM cell, the magnetic tunnel junction is where spin physics meets process engineering. imec identifies cobalt-iron-boron (CoFeB) for the fixed and free ferromagnetic layers and magnesium oxide (MgO) for the tunnel barrier as a second major breakthrough after the discovery of spin-transfer torque. This combination substantially increased tunnel magnetoresistance and improved switching efficiency, giving circuits a clearer read margin and a more practical write operation.
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- Supplier Device Package 8-DFN-EP, Small Flag (5x6)
- Base Product Number MR25H10
- Package / Case 8-VDFN Exposed Pad
- Operating Temperature -40°C ~ 85°C (TA)
- Clock Frequency 40 MHz
Perpendicular magnetic anisotropy then allowed the useful magnetization direction to stand out of the wafer plane. Compared with in-plane designs, that architecture helped researchers pursue smaller junctions while preserving the thermal stability needed for data retention.
IBM’s reported 2016 result illustrates the engineering progress, not a universal product specification: 11 nm junctions switched with 7.5 microamperes using 10-nanosecond pulses. IBM researcher Daniel Worledge described a write-error rate of 7×10−10 under those conditions. Such figures came from a particular research configuration and should not be read as the guaranteed performance of every commercial part.
When did STT-MRAM become commercial?
Commercialization happened gradually through products that valued nonvolatility, endurance and density more than the absolute minimum write latency. imec’s history places early products around 2015, first as nonvolatile buffers for DRAM and SSD systems and later as replacements for embedded Flash. Everspin’s 2019 Form 10-K gives a narrower corporate milestone: its STT-MRAM production started in 2017, and 256 Mb and 1 Gb densities were shipping when the filing was made.
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errorsThe applications cited in that filing and in IBM’s later summaries include:
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- Package / Case 8-VDFN Exposed Pad
- Supplier Device Package 8-DFN (5x6)
- Base Product Number MR25H256
- Operating Temperature -40°C ~ 85°C (TA)
- Write Cycle Time - Word, Page -
- SSD write buffers, where persistence can protect or stage data during power interruptions;
- persistent-memory cards;
- fabric accelerators and other data-center equipment;
- embedded nonvolatile memory in microcontrollers, as an alternative to embedded Flash in suitable designs; and
- standalone 1 Gb memory devices for buffering and other system roles.
Everspin reported interfaces derived from standard DDR3 and DDR4 conventions. It also warned that some customers could need controller changes, an important reminder that adopting a memory technology involves system firmware and validation as well as the memory die.
How STT-MRAM compares with SRAM and Flash
There is no single apples-to-apples benchmark in the cited material covering all current products. The meaningful comparison depends on the workload and on whether the memory is used as a cache, a buffer or embedded storage.
| Characteristic | STT-MRAM | SRAM | Flash |
|---|---|---|---|
| Data retention | Nonvolatile magnetic state | Volatile; needs power to hold data | Nonvolatile charge-trap or floating-gate state |
| Standby behavior | Can retain data without refresh power | Standby leakage is a major design concern | Retains data without power, but is generally managed in larger erase/program units |
| Write operation | Current through the MTJ switches the free layer; speed, energy and barrier stress must be balanced | Very fast electrically, but volatile | Program and erase operations are slower and subject to endurance limits |
| Density potential | Perpendicular designs and small junctions support high density; a 5 nm cache analysis modeled a cell at 43.3% of the SRAM macro area | Fast but area-intensive for large capacities | High density, commonly used for bulk nonvolatile storage |
| Integration | Requires magnetic-stack deposition, patterning, testing and CMOS-compatible process integration | Uses established CMOS logic processes | Uses specialized nonvolatile process modules |
| System interface | Commercial parts can use DDR3- or DDR4-derivative interfaces; controller changes may still be required | Usually integrated directly into processor or SoC logic | Often requires a flash controller for translation, error management and wear handling |
The table describes architectural trade-offs rather than a current product ranking. The reviewed sources do not establish a current market-share figure or a complete inventory of available devices.
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Last-level cache is plausible in modeling
imec’s 2018 IEDM analysis evaluated STT-MRAM for a 5 nm last-level cache using design-technology co-optimization and silicon-verified models. It reported a modeled cell area equal to 43.3% of the SRAM macro area and an energy-efficiency benefit for high-density cells. This was a feasibility analysis, not a measured commercial processor cache.
L1 and L2 caches demand faster writes
Processor L1 and L2 caches operate on much tighter latency budgets. imec describes STT-MRAM writing as relatively inefficient and slow compared with SRAM. Increasing the write current to accelerate switching places more stress on the thin MgO barrier, which can reduce endurance. The combination of fast-switching energy, write latency and reliability made the analyzed STT-MRAM form unsuitable for sub-nanosecond L1/L2 requirements.
IBM’s long-term ambition has nevertheless been to make spin-torque memory dense and fast enough for server cache. Worledge stated in 2016 that the technology could replace combinations of SRAM and Flash in some ultra-low-power, medium-performance mobile and Internet-of-Things applications, while describing server cache as a continuing goal. That statement expressed a research direction, not evidence that server-cache adoption had occurred.
What manufacturing had to solve
A laboratory MTJ becomes an industry product only when its magnetic layers, barrier and switching transistors can be fabricated with repeatable yields on large wafers. imec describes CMOS-compatible 300 mm integration flows for multiple MRAM variants, showing the role of research institutes in adapting spintronic stacks to semiconductor process rules.
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Everspin’s fiscal-year 2019 filing said its STT-MRAM products were produced in GLOBALFOUNDRIES 300 mm facilities and described a licensing relationship that allowed GLOBALFOUNDRIES to offer embedded MRAM. That filing is a historical corporate disclosure; it does not establish that the same manufacturing arrangements or product portfolio remain current. The same document’s note about possible controller modifications highlights another part of the bridge from research to industry: customers must qualify interfaces, firmware, packaging, testing and system reliability, not just the memory cell.
The practical legacy of the technology
STT-MRAM’s industrial significance is not that one magnetic device suddenly replaced every other memory. Its significance is that a chain of advances connected a spintronic switching mechanism to semiconductor economics: MgO and CoFeB improved the junction, perpendicular anisotropy enabled scaling, low-current research reduced the write burden, product-level demonstrators established yield targets, and 300 mm CMOS integration made foundry production conceivable.
That chain produced real memory products and defined credible roles in buffers, persistent-memory devices, accelerators and embedded nonvolatile memory. It also clarified the remaining boundary: STT-MRAM can offer an attractive combination of retention, endurance and density, but the current, speed and barrier-reliability trade-offs still matter most where SRAM’s sub-nanosecond cache behavior is required.
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