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A silicon quantum processor stores quantum information in the spin of an electron confined inside a nanoscale silicon quantum dot. Electrostatic gates hold and tune the electron, microwave or electric fields rotate its spin, and a nearby charge sensor converts the spin-dependent result into a classical bit. Two-qubit gates briefly couple neighboring dots so their spins become entangled.
The same chip must operate inside a cryogenic control system, repeatedly calibrate its pulses, measure thousands or millions of outcomes, and suppress errors well enough for quantum-error-correction codes to create reliable logical qubits. Silicon is attractive because it can use highly developed CMOS manufacturing and isotopically purified material, but a commercially useful, fault-tolerant silicon processor has not yet been demonstrated.
What a silicon quantum processor is
A silicon spin processor is a collection of quantum dots. Each dot is a tiny potential well made by voltages on metal gates above a silicon device layer. In the simplest configuration, one dot confines one electron. The electron cannot be treated like an ordinary digital charge carrier: its spin has two quantum states that form the computational basis, conventionally written as |0> and |1>.
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A qubit can occupy a superposition of those states and can become entangled with another qubit. A measurement produces one classical result, 0 or 1, with probabilities determined by the qubit state. The processor therefore combines analog quantum control with conventional electronics that generate pulses, collect sensor signals and run calibration and decoding software.
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Quantum-dot hardware
Gate electrodes define the dot, set its electron number, change its energy and control how strongly it couples to a neighboring dot. A common silicon metal-oxide-semiconductor (SiMOS) design uses a double dot containing two electrons. An exchange gate between the dots changes the interaction between their spins; that interaction is the basis of an electrically controlled entangling operation.
Spin states and charge sensing
Spin itself is difficult to measure directly. During readout, the device converts spin information into a charge movement that a nearby radio-frequency single-electron transistor (RF-SET) can detect. The sensor’s analog response is amplified and classified as a digital result. The 2024 Nature demonstration using this arrangement reported high-fidelity initialization and readout while operating above 1 kelvin.
How one computation proceeds
A useful way to understand the processor is to follow one complete control cycle. The details vary by device, but the sequence below describes the operations used in silicon spin experiments.
- Prepare the dots. Gate voltages load the required number of electrons and separate the desired spin state from unwanted charge configurations. Initialization sets a known starting state before a circuit runs.
- Apply calibrated pulses. The control system sends microwave or electrically generated radio-frequency pulses with precisely chosen amplitude, phase and duration. These pulses implement rotations of individual spins and interactions between neighboring spins.
- Entangle selected qubits. Increasing exchange coupling, or using a related electrically controlled interaction, lets two spins evolve jointly. The pulse duration determines the intended two-qubit gate angle.
- Measure. A readout sequence maps spin-dependent behavior onto a charge signal. The RF-SET records the signal, and classical electronics assign a 0 or 1.
- Calibrate again. Software compares measured outcomes with expected calibration results, then updates pulse parameters, gate voltages or sensor thresholds. This feedback is essential because charge offsets, drift and noise change during operation.
Quantum algorithms repeat this cycle many times. A single run gives one sample, so the processor executes the same circuit repeatedly to estimate output probabilities. Classical control hardware handles timing, data acquisition and, eventually, real-time error decoding.
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How gates are controlled in silicon
Single-qubit rotations
A single-qubit gate rotates the electron’s spin on its Bloch sphere. The processor drives the spin at its resonance frequency with a magnetic field or with an electrically driven mechanism that produces an effective oscillating field. Frequency, phase, amplitude and pulse length determine the rotation. A calibrated pulse can implement a quarter-turn, a half-turn or an arbitrary angle rather than only a digital on/off operation.
Two-qubit entangling gates
Two neighboring spin qubits interact through exchange coupling. An exchange gate changes the tunnel coupling and electrostatic conditions between dots, allowing the spins to acquire a controlled relative phase or to swap spin information. Properly timed exchange pulses create an entangling gate; without such a gate, a processor could perform only independent single-qubit rotations.
Calibration and benchmarking
Control is not a one-time setup. Engineers run calibration sequences to determine resonance frequencies, pulse amplitudes, exchange timing, readout thresholds and leakage rates. Randomized benchmarking and related protocols estimate average gate performance without requiring the device to reproduce a particular algorithm. A Nature Physics study found repeatable two-qubit fidelity above 99% and connected the remaining errors to slow nuclear and electrical noise as well as to the applied control sequence. Another Nature Communications experiment used adaptive noise suppression to raise single-qubit gate fidelity above 99.6%.
What has been demonstrated at cryogenic temperatures
Silicon spin qubits need refrigeration because thermal energy would otherwise overwhelm the small energy differences used to define and control their states. The exact temperature depends on the device and operation. A 2024 Nature experiment demonstrated readout and initialization fidelity as high as 99.34%, single-qubit Clifford fidelity up to 99.85% and two-qubit fidelity of 98.92% while operating above 1 kelvin. “Above 1 K” does not mean the processor works at room temperature: the chip remains in a cryogenic system, with specialized wiring, filtering and amplifiers.
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Operating above 1 kelvin is significant because higher-temperature stages can offer more cooling power and simplify some control electronics. It does not remove the need for cryogenics, nor does it establish that every silicon-qubit design will reach the same temperature or fidelity. Results from a few-qubit device should not be read as a specification for a future million-qubit machine.
Why researchers use silicon
- Low magnetic noise in enriched material. Natural silicon contains silicon-29 nuclei with nonzero spin. Isotopically enriched silicon reduces the concentration of those nuclei and therefore suppresses an important source of magnetic noise.
- Small physical devices. Quantum dots can be roughly 100 nanometres across in advanced demonstrations, allowing many devices to fit on a wafer.
- CMOS-compatible processing. Silicon quantum dots use fabrication steps related to those developed for conventional semiconductor manufacturing. This creates a path to larger wafers, automated process control and integration with classical electronics.
- Potentially long-lived spin information. Electron spin can retain quantum information for relatively long periods when magnetic and electrical noise are controlled, although useful algorithm performance also depends on gate speed, leakage and measurement quality.
Intel’s 300 mm wafer study reported 99.9% single-qubit gate fidelity on devices about 100 nm across. The result is a fabrication and control demonstration, not evidence that a complete fault-tolerant processor can already be manufactured at that scale. A separate Nature wafer report emphasized that millions of physical qubits will require semiconductor-industry-scale fabrication and cryogenic testing.
Where errors come from
Every physical qubit is imperfect. Silicon devices face several distinct failure mechanisms:
- Nuclear-spin noise: residual silicon-29 nuclei and other magnetic sources shift the electron’s resonance frequency.
- Electrical and charge noise: fluctuating charges alter dot energies and tunnel barriers. Electrical noise can be converted into effective magnetic noise during electrically driven control.
- Device variability: microscopic differences in interfaces, oxides and gate dimensions mean that two nominally identical dots may need different operating voltages and pulse parameters.
- Drift: resonance frequencies, sensor responses and charge offsets change over minutes or hours, requiring recalibration.
- Pulse imperfections: timing, amplitude and phase errors leave a rotation short of its target; an exchange pulse can also over-rotate or under-rotate.
- Leakage: population can leave the intended two-level qubit space, for example by occupying an unwanted orbital or charge state.
- Readout and initialization mistakes: the sensor can misclassify a charge signal, or preparation can begin in the wrong spin state.
Improving one metric does not automatically improve all the others. A device may have excellent single-qubit rotations but weaker two-qubit gates, or accurate gates but inadequate measurement speed. Error budgets must therefore be measured for the complete operating sequence.
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How quantum error correction creates a logical qubit
Quantum error correction does not make an individual physical qubit flawless. Instead, it spreads one logical qubit across many physical qubits and repeatedly checks for errors. Additional qubits, called ancillas, interact with the data qubits. Measuring the ancillas reveals an error syndrome—information about whether an error occurred and where—without directly revealing the logical qubit’s encoded value.
Syndrome extraction and decoding
- Prepare ancilla qubits in known states.
- Apply a prescribed pattern of one- and two-qubit gates between ancillas and data qubits.
- Measure the ancillas. Their outcomes form a syndrome.
- Send the syndrome to a decoder, which uses the history of results to infer the most likely error.
- Apply a correction, or track it in software as a “Pauli frame” so later operations interpret the state correctly.
These checks run in repeated cycles because errors can occur between measurements. A practical code must tolerate faulty gates, faulty measurements, leakage and loss of synchronization. The selected code has a threshold: below a certain physical error rate, increasing the code size can reduce the logical error rate; above it, adding qubits makes the encoded result worse.
Engineering conditions for a useful code
A silicon architecture must sustain physical gate and measurement performance below the chosen code threshold, not merely achieve a high score in one isolated experiment. It also needs enough connectivity to execute syndrome circuits, a way to move or couple qubits, uniform control across a large array, fast measurement and a decoder that keeps pace with the hardware. A 300 mm foundry study reported more than 99% single- and two-qubit control fidelity across four devices and up to 99.9% state-preparation and measurement fidelity. Those figures support the engineering case for scaling, but they do not constitute a demonstrated fault-tolerant logical processor.
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Silicon spin qubits compared with other approaches
The following comparison separates the physical mechanism from the maturity of a scaled architecture. Values described as “not stated” were not specified for the cited silicon demonstrations.
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| Comparison point | Silicon spin qubit | Superconducting circuit qubit |
|---|---|---|
| Physical encoding | Electron spin states in a silicon quantum dot | Quantum states of a fabricated superconducting circuit |
| Typical control mechanism | Resonant magnetic or electric-drive pulses; exchange coupling for entangling gates | Microwave control with circuit-mediated coupling |
| Readout | Spin-to-charge conversion followed by charge sensing, such as an RF-SET | Microwave response of a coupled resonator or related circuit |
| Temperature | Cryogenic; operation above 1 K with the cited 2024 fidelities | Cryogenic; the exact value depends on the hardware and was not stated in the supplied silicon demonstrations |
| Physical size and fabrication | Dots about 100 nm in a 300 mm-wafer study; CMOS-related processing | Larger circuit structures made with superconducting thin films |
| Connectivity and wiring | Neighbor coupling is natural, but dense gate and sensor wiring is a scaling challenge | Couplers and microwave wiring provide connectivity but create their own routing and packaging limits |
| Demonstrated silicon fidelity | Up to 99.85% single-qubit Clifford, 98.92% two-qubit, and 99.34% readout/initialization in the cited above-1-K experiment | Not stated in the cited silicon-focused results |
| Fault-tolerant status | No full-scale, commercially available fault-tolerant processor demonstrated | Not determined by the silicon experiments summarized here |
High fidelity in a few-qubit experiment is an important milestone, but it is different from a scaled architecture with millions of physical qubits, stable calibration and a logical error rate that improves as the code grows.
Scaling beyond a few dots
Fabrication and cryogenic testing
A large processor must reproduce dot dimensions, tunnel barriers, sensor characteristics and control response across an entire wafer. Each device then needs cryogenic characterization, because room-temperature electrical tests cannot fully predict low-temperature charge stability or spin performance. Wafer-scale studies are intended to make this testing repeatable rather than dependent on hand-tuning a few laboratory devices.
Connectivity and shuttling
Nearest-neighbor exchange is straightforward, but algorithms may require interactions between qubits that are not adjacent. Architectures can add coupling structures, route control signals or physically move electrons between dots. SpinBus-style shuttling is a proposed scaling architecture for transporting spin qubits; it is not a deployed product or a demonstrated full processor. Any shuttling scheme must preserve the spin state while moving it and must avoid adding errors faster than the connectivity benefit justifies.
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Millions of physical qubits imply millions of control parameters, sensor channels and calibration records. Conventional electronics must generate synchronized pulses, digitize readout, identify leakage, update calibrations and supply syndrome data to a decoder. Heat deposited by wiring and amplifiers is itself a constraint at cryogenic stages, so scaling is a system-engineering problem rather than simply a matter of printing more dots.
What the technology can and cannot do now
Current silicon research has established high-fidelity one- and two-qubit operations, wafer-scale fabrication experiments and early approaches to moving or connecting spin qubits. These results show that the basic ingredients—confinement, control, measurement and repeatable manufacturing—can work together. They do not show a commercially available silicon quantum computer that runs large algorithms with fault-tolerant protection.
The next milestones are sustained performance across much larger arrays, automated cryogenic tuning, reliable two-qubit connectivity, fast and accurate syndrome measurement, and logical qubits whose error rates fall as more physical qubits are added. Until those tests are passed, claims about useful scale should be treated as architecture proposals or laboratory demonstrations rather than finished products.
A concise mental model
Think of a silicon quantum processor as a dense array of controllable electron traps. Voltages place and tune the electrons; resonant pulses rotate their spins; exchange coupling entangles neighbors; a charge sensor reads them; and a classical feedback system continually recalibrates the hardware. Error-correction circuits then use extra qubits and repeated measurements to detect, decode and correct faults. Silicon’s manufacturing advantages make that array promising, while cryogenic operation, wiring, variability and the large overhead of error correction remain the central engineering barriers.
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