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Semiconductor test systems verify chips by applying controlled electrical signals, measuring each device’s response, and comparing the results with limits derived from the chip’s design and specifications. Automated test equipment (ATE) performs this work first on unpackaged dies at wafer level and again on packaged chips. Probers, probe cards, handlers, sockets, temperature-control hardware and test software form one coordinated production system that accepts, grades or rejects devices before shipment.
Wafer test catches many defective dies before packaging; package final test checks the assembled product under its intended electrical and, when required, temperature conditions. Burn-in and system-level test can add stress or application-context coverage for products whose reliability or software interactions justify those extra stages.
What semiconductor test systems actually verify
A chip is not approved because it merely powers on. A production test program sends defined patterns and electrical conditions to the device, measures outputs and operating characteristics, and compares every result with an expected value or specification limit. The system then classifies the unit as passing, failing or, in some products, belonging to a performance grade.
Advantest describes ATE as “a highly integrated system that combines a tester for precise signal processing, peripheral equipment that handles the semiconductor devices being tested, and software that controls and coordinates these elements.” That division explains why a semiconductor test floor contains more than a box labeled tester: connection hardware and device-handling equipment are part of the measurement system.
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The exact coverage depends on the device. A memory chip, power semiconductor, analog or radio-frequency device and system-on-chip (SoC) have different electrical limits, timing behavior and functional requirements. Advantest’s semiconductor-test overview and product portfolio describe separate configurations for these device classes (Advantest semiconductor test overview; Advantest ATE portfolio).
The production flow from wafer to shipment
1. Convert design expectations into a test program
Engineers build the test program from integrated-circuit design data, datasheets and production limits. It defines the input signals, power conditions, timing relationships, measurements, pass/fail limits and any grading rules. The program also controls the sequence of tests and communicates with the prober or handler so each device is contacted, tested and removed safely.
In a typical ATE cycle, the tester generates signals, the device responds, measurement instruments capture the response, and software compares it with reference values. The result is stored for that die or package and used to sort it. Advantest explains this program-to-measurement workflow in its ATE explainer (What Is ATE?).
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2. Probe the wafer before dicing
After front-end wafer processing, the wafer is placed on a prober stage. A probe card carries fine needles or other contacts that touch the electrode pads of individual dies. The prober moves the wafer so each die lines up with the probe card, while the tester applies power and signals through that temporary electrical path.
Wafer probing can include temperature control and records a map of results by physical wafer position. The map identifies passing and failing dies before the wafer is diced, allowing assembly operations to use known-good material more efficiently. Advantest’s prober information describes this positioning and contact role (Advantest prober), while its annual-report explainer details wafer-level semiconductor testing (Advantest Integrated Annual Report 2022, Semiconductor Test Systems explainer).
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A wafer-level pass is not a guarantee that the eventual packaged chip will pass. Packaging introduces assembly materials, bonds, leads, solder or other interfaces that require their own verification, so final test remains a distinct production screen.
3. Assemble and package the die
Passing dies are separated from the wafer and assembled into packages. Packaging protects the silicon and provides the external pins, balls or pads used by a circuit board or system. The package changes the physical and electrical path to the die, which is why the next test stage uses different contact hardware and often a different handling sequence.
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In final test, a handler presents packaged devices to a socket, contactor or other device interface. The tester applies the programmed signals and measures the package’s behavior; the handler may control the device temperature and routes each unit according to the result. Good units can be separated from failures, and products with qualified performance grades can be binned accordingly.
Teradyne describes coordinated wafer and package test cells in which ATE, handlers, probers, contactors and related equipment operate as an integrated production solution (Teradyne test-cell solutions). The physical interface must match the package’s dimensions, pinout, contact force and electrical requirements; a capable tester cannot compensate for an incompatible socket or probe card.
5. Add burn-in or system-level test when the product requires it
Burn-in deliberately stresses selected devices, commonly with elevated temperature and voltage, to expose some defects that may appear early in a product’s life. It is a reliability screen for specified risks, not proof that every future failure mode has been eliminated. Advantest identifies burn-in as an additional test method rather than a universal step for every chip (Advantest ATE explainer).
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System-level test (SLT) exercises a chip in an environment closer to its end use. Teradyne describes SLT as a process after wafer and package ATE that can run software and observe interactions among intellectual-property blocks and operating domains (Teradyne System Level Test). SLT can reveal integration or workload issues that narrow parametric measurements do not, but its inclusion depends on the device, risk profile and production economics.
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| Test category | What is measured | Typical purpose |
|---|---|---|
| Continuity and structural checks | Open connections, shorts and other basic electrical paths | Find assembly or interconnect problems before deeper testing |
| Parametric electrical tests | Input/output voltage and current, leakage, drive levels and related electrical characteristics | Confirm operation stays within specified limits |
| Timing tests | Propagation, setup/hold or other timing relationships defined for the device | Verify that signals move and are captured within required windows |
| Functional tests | Responses to instruction, logic, memory or application-specific patterns | Check that the semiconductor behaves as designed |
| Temperature-dependent tests | Electrical and functional behavior at controlled temperatures | Qualify operation across the product’s specified range |
| Burn-in | Behavior while exposed to defined thermal and voltage stress | Expose some early-life, stress-induced defects |
| System-level test | Software execution and interactions among blocks or operating domains | Check integration in a more user-like context |
Advantest distinguishes parametric tests, which can identify shorts, disconnections and electrical values, from function tests that assess whether the device behaves as designed. Its overview also identifies function, timing and electrical-characteristic testing as core categories (Advantest semiconductor test overview). A production program selects only the measurements relevant to the device and its qualification requirements; no single checklist applies to every semiconductor.
The equipment that makes a test cell work
| Equipment | Role in verification | Where it is used |
|---|---|---|
| ATE tester | Generates precision signals, supplies power, measures responses and evaluates results against limits | Wafer, package and sometimes system-level test |
| Prober | Aligns and moves the wafer so individual dies contact the probe card | Wafer test |
| Probe card | Provides the temporary electrical contacts to die electrodes | Wafer test |
| Handler | Loads, transports, heats or cools and sorts packaged devices | Package final test |
| Socket, contactor or device interface | Connects package pins, balls or pads to the tester | Package final test |
| System-level test equipment | Runs software and application-like workloads while monitoring the device | Additional post-ATE coverage |
| Test software and data systems | Controls sequences, applies limits, records measurements and drives grading or wafer maps | All automated stages |
Teradyne’s semiconductor-testing portfolio presents these components as coordinated solutions rather than isolated instruments (Teradyne semiconductor testing). Interface compatibility is a practical requirement: the tester, probe card, prober, handler, socket and contactor must agree on mechanical dimensions, electrical bandwidth, temperature range and control protocols.
How devices are judged and sorted
For every measurement, the test program defines an expected value, an allowable range or a pass/fail rule. Software records the result with the die’s wafer coordinates or the package’s serial or lot identity. A device outside a required limit is rejected or sent to a designated failure bin; a passing device may be assigned a performance grade if the product has multiple qualified speed, power or other bins.
Sorting is not the same as proving perfection. Production tests sample the behaviors and conditions defined by the specification and test strategy. Burn-in and SLT extend coverage for particular reliability or integration risks, but neither establishes that every possible defect has been found. There is no universal published percentage for rejected chips, defect escapes or test yield that applies across semiconductor products; those outcomes vary by process, design, limits, lot and manufacturer.
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Wafer sort versus package final test
| Characteristic | Wafer sort (probe) | Package final test |
|---|---|---|
| Device state | Unpackaged dies still on the wafer | Dies assembled into finished packages |
| Primary interface | Probe-card needles or contacts touching die electrodes | Socket, contactor or device interface touching package terminals |
| Positioning hardware | Prober stage and wafer alignment | Handler and package transport |
| Typical data output | Pass/fail results mapped to wafer locations | Per-package results, bins and shipment eligibility |
| Main business purpose | Avoid packaging dies that already fail defined criteria | Verify the assembled product and separate good units from failures |
| What a pass means | The die met wafer-level criteria under the programmed conditions | The packaged device met final-test criteria under the programmed conditions |
These stages complement one another. Wafer sort reduces wasted packaging effort, while final test catches package-related and post-assembly issues and confirms the shipped form factor.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Choosing a test strategy for a chip
Manufacturers do not choose a test system by tester brand alone. They match the complete cell to the device, measurements and production targets.
- Start with the test stage: specify wafer probe, package final test, burn-in or SLT, because each requires different handling and contact hardware.
- Match the device class: SoC, memory, power, analog/RF and other devices have different signal, current, voltage, timing and thermal requirements. Advantest lists device-specific ATE offerings (Advantest semiconductor test systems).
- Define measurement coverage: include required function, timing, electrical parameters and operating temperatures rather than buying unused capability.
- Model production performance: compare throughput, parallelism, test coverage, equipment footprint and cost of test. Advantest identifies throughput and footprint as important differentiators, but the best balance depends on the product and factory.
- Verify interface fit: check electrical bandwidth, current delivery, contact wear, package dimensions, thermal control and software compatibility across tester, prober or handler and contact hardware.
- Plan data handling: retain wafer maps, package results, bins and lot identity so failures can be traced to a process step or equipment condition.
Common failure points and practical fixes
Unstable or intermittent contact
Probe needles, sockets and contactors can wear, become contaminated or lose alignment. Symptoms include intermittent opens, unexplained retests and results that change when a device is repositioned. The corrective path is to inspect and clean the interface according to its maintenance procedure, verify alignment and contact force, and run a known-good reference device before blaming the silicon.
Temperature not representative of the test condition
A device can pass at room temperature but fail at a specified hot or cold condition, or the reverse. Confirm that the prober or handler has reached the programmed temperature, allow adequate stabilization time and verify that the sensor measures the device location rather than only the chamber air.
Limits or patterns that do not match the design
Incorrect reference values, timing windows or power limits can create false rejects or let marginal units pass. Tie each limit to the approved design and specification data, version the test program and review changes through engineering control.
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Insufficient coverage for system interactions
Parametric and functional ATE can miss issues that appear only when software drives several blocks together. Where that risk matters, add SLT coverage designed around the actual workloads and interfaces; do not assume that a longer version of the same pin-level test automatically provides system-level coverage.
Assuming wafer results predict package results
Wafer maps are valuable for die quality and process analysis, but they cannot replace package final test. Keep the stages separate in the release criteria and investigate failures that first appear after assembly.
What “verified before shipment” means
A chip is shipment-eligible when it has completed the test stages required for its product and lot, met the programmed electrical, timing and functional limits, and been assigned the appropriate pass or grade record. The result is evidence of compliance with defined tests—not a claim that every possible defect or future field condition has been eliminated.
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