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A semiconductor fab turns a polished, ultra-pure silicon wafer into many tested integrated-circuit die by repeatedly adding films, drawing microscopic patterns, removing selected material, changing silicon’s electrical properties, cleaning, and flattening the surface. The finished wafer is electrically probed, cut into individual die, packaged for power, heat and signal connections, and tested again before shipment.
That sequence is the front end of chip manufacturing. Chip design supplies the circuit blueprint; the fab transfers it to wafer after wafer; back-end assembly and test turn those wafer patterns into a product that can be installed in a computer, phone, vehicle or other system.
What a semiconductor fab actually does
A fab is the facility and process flow used for front-end wafer fabrication. It does not begin with a loose collection of transistors. It begins with a circular slice of ultra-pure, single-crystal silicon that has been polished to an extremely smooth surface. Every later operation must preserve that surface’s cleanliness, thickness and alignment while building structures far too small to see unaided.
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- Form physical structures: insulating, semiconducting and conducting films become transistor regions and the metal layers that connect them.
- Control electrical behavior: selected silicon regions receive carefully measured impurities, and each layer is patterned and aligned to the layers beneath it.
The front end creates complete die across the wafer. The back end separates those die, attaches them to packages, provides thermal and mechanical support, makes external electrical connections, and screens the finished devices.
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| Stage | What it produces | Typical checks |
|---|---|---|
| Front-end fabrication | Transistors and interconnect layers on a silicon wafer | Film thickness, pattern alignment, defects and electrical probes |
| Back-end assembly and test | Individual packaged chips ready for a system | Die attach, connections, heat path, burn-in and electrical/platform validation |
The repeating process modules
Although a modern process route can contain thousands of individual operations, most belong to a small set of modules. The modules are repeated in different materials, dimensions and sequences as the circuit is built.
Deposition and oxidation add films
Deposition places a thin film on the polished wafer. A film may be insulating, semiconducting or conducting, depending on the layer’s role. Oxidation grows an insulating film from the silicon surface. The new layer is deliberately uniform because later patterning transfers dimensions measured in tiny fractions of a human hair.
Photoresist creates a temporary stencil
The wafer is coated with a uniform, light-sensitive material called photoresist. In a positive resist, exposure makes selected areas easier to remove during development; in a negative resist, exposure makes selected areas remain. The resist choice changes which regions are protected in the next operation.
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Lithography places the pattern
A photomask or reticle carries the circuit image. Ultraviolet light projects that image onto the resist. After chemical development, the remaining resist is a temporary stencil: it exposes the regions that must be removed or modified and protects the regions that must stay. The Semiconductor Industry Association describes photolithography as stenciling new patterns with light.
Etching transfers the pattern into the film
Etch removes exposed material while the resist protects the selected features. Wet etching uses liquid chemicals. Dry or plasma etching uses reactive gases, and may also use physical bombardment. Dry methods can provide tighter control and contamination performance for demanding patterns. The resist is stripped after the transfer, and the wafer is cleaned before another module begins.
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| Operation | Primary action | Why it matters |
|---|---|---|
| Deposition or oxidation | Adds or grows a film | Provides the material that will become part of a device or interconnect |
| Etching | Removes selected material through the resist-defined pattern | Leaves trenches, openings, lines or other three-dimensional features |
Doping changes silicon’s electrical behavior
Pure silicon does not provide all the electrical regions a transistor needs. Doping introduces controlled impurities such as boron or arsenic so different areas have different carrier behavior.
Two broad approaches are used:
- Diffusion: furnace processes introduce dopants at the surface and drive them into silicon thermally. OSHA describes a predeposition step followed by a drive-in step.
- Ion implantation: dopant atoms are ionized, accelerated by an electric field and embedded in the wafer. The dose and energy determine how many ions enter and how deep they travel.
An anneal then activates dopants electrically and repairs or redistributes the implanted material. Implantation offers precise dose and depth control; furnace diffusion relies on thermal movement and is useful where that profile is appropriate.
Cleaning and chemical-mechanical polishing reset the surface
Residues from deposition, exposure, etch and implantation must be removed before they interfere with the next layer. Chemical-mechanical polishing, often called CMP, removes excess material and flattens the wafer. A flat surface is essential because the next lithography layer must focus and align across the wafer without inheriting bumps from earlier layers.
How the fab builds a transistor and its wiring
The first patterned layers define device regions in or on the silicon. Repeated deposition, lithography, etch, doping, anneal, cleaning and polishing steps form the transistor structures, including the regions that control current flow and the insulating boundaries around them.
Once the device layer is complete, additional layers build the interconnect network. Conductive films are patterned into lines and contacts; insulating films separate one wiring level from another; openings and vertical connections link the levels. The same pattern-transfer discipline applies to both transistor features and metal routing, even though the materials and dimensions change.
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Alignment is cumulative. Each new reticle image must register with features already present, so inspection and measurement between modules detect drift before it propagates through hundreds of later operations.
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- Prepare the wafer. Start with a circular wafer made from ultra-pure, single-crystal silicon. Polish it to a very smooth surface suitable for device processing.
- Grow or deposit a film. Add the insulating, semiconducting or conducting material required for the next patterned layer.
- Coat with photoresist. Spin or otherwise apply a uniform light-sensitive coating across the wafer.
- Expose and develop. Align the photomask or reticle, project ultraviolet light, then chemically develop the resist so the selected regions are open or protected.
- Etch the exposed material. Use a wet chemical or dry/plasma process to transfer the resist image into the film beneath it.
- Dope and anneal where required. Introduce impurities by diffusion or ion implantation, then anneal to activate and position the dopants.
- Strip and clean. Remove the used resist and process residues so contamination does not carry into the next module.
- Planarize. Use chemical-mechanical polishing to flatten the surface and remove unwanted material.
- Repeat for device and interconnect layers. Run the modules again, with new masks and materials, until the transistor structures and metal wiring are complete.
- Inspect and probe the wafer. Inspect patterns and defects, then electrically probe die to identify those meeting specifications and to monitor process drift.
- Dice, package and validate. Separate the wafer into die, attach each die to a package substrate, fill microscopic gaps with epoxy, attach a lid or heat spreader, and run burn-in and final electrical/platform tests.
Why the loop is repeated so many times
A chip is not made by exposing one master image once. Transistors require multiple patterned films and modified silicon regions, while interconnects require many alternating conductor and insulator layers. Each layer has its own deposition, resist, lithography, development, etch, clean and planarization requirements.
The Semiconductor Industry Association says front-end steps can be repeated several hundred times. ASML describes the full route as thousands of steps and more than three months from design to production. That duration includes repeated processing, measurement, rework decisions and queue time between specialized tools; it is not the exposure time of one wafer.
Wafer inspection, yield and chip count
Yield is the percentage of die on a processed wafer that are usable and meet specification. It is a manufacturing result, not a guaranteed count. Defects can make individual die fail, and the probability of a defect affecting a die rises with die area. For a given defect density, a smaller die generally allows more usable die than a larger die, although smaller features demand tighter patterning and process control.
A U.S. government semiconductor-fabrication overview gives an illustrative figure: a 300 mm wafer might produce 600 or more chips. The number varies with the die design, die area, edge exclusion, scribe lanes and defects, so the figure must not be treated as a universal output.
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| Measure or example | What the figure means |
|---|---|
| 300 mm wafer | Example wafer diameter used in the government overview |
| 600 or more chips | Illustrative possible die count from that wafer; actual usable output depends on design and defects |
| Several hundred front-end repetitions | Scale of repeated processing modules described by the Semiconductor Industry Association |
| Thousands of steps; more than three months | ASML description of the overall route from design to production |
Electrical probing happens while the die are still part of the wafer. Test data can map failing locations, separate known-good die from failures and reveal process changes that require correction before more wafers are run.
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Dicing separates the die
The completed wafer is cut along designated lanes so each circuit becomes an individual die. Edge regions and the cut lanes do not become functional chips, which is one reason the simple geometric die count overstates the usable total.
Assembly creates a usable package
Each selected die is attached to a package substrate. Epoxy can fill microscopic gaps, and a lid or heat spreader is attached to provide a controlled path for heat. The package protects the silicon, supplies mechanical support and carries electrical connections between the die and the circuit board or socket.
Burn-in and final tests screen finished devices
Intel describes high-voltage and high-temperature burn-in, followed by electrical testing and process-platform validation that simulates customer conditions. These package-level checks are different from wafer probing: wafer test screens die before separation, while burn-in and final validation exercise the finished device and its package.
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Does lithography carve the wafer?
No. Lithography creates a resist image. Etch performs the material removal, and doping or implantation changes electrical properties in selected regions. Lithography is the pattern-definition step that tells those later operations where to act.
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Are deposition and etch opposites?
They are complementary rather than interchangeable. Deposition or oxidation supplies a film; etch selectively removes part of that film after lithography defines the protected and exposed areas.
Is a process node a literal transistor measurement?
Not necessarily. Intel describes a node as a process recipe and set of specifications. Node names should not be read as a single guaranteed physical dimension for every transistor or wire. Exact feature sizes, fab locations, equipment capabilities and commercial availability depend on the specific process and require current verification.
Why can two wafers of the same diameter produce different numbers of chips?
Die area, circuit shape, edge losses, scribe lanes and defect locations all change the number of usable die. Wafer diameter alone does not determine output.
The practical mental model
Think of a fab as a controlled layer-building loop rather than a machine that stamps out a finished processor. A wafer enters as polished silicon. Films are added, a mask and light define a temporary pattern, exposed material is removed or modified, residues are cleaned, and the surface is flattened. That loop is applied repeatedly until three-dimensional transistor structures and a multilayer wiring network exist. Inspection and electrical tests then determine which die survive, and packaging turns those die into protected, connected components.
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