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There is no defensible single “best” foundry for advanced AI chips from the public evidence available. TSMC documents the most mature combination of leading-edge logic and AI-oriented packaging; Samsung emphasizes coordinated foundry, memory, and package integration; Intel Foundry combines its 18A RibbonFET and PowerVia process with Foveros, EMIB, and a broader “systems foundry” model. Those are different strengths, not a like-for-like ranking of yield, price, capacity, or customer adoption.
The practical choice depends on the accelerator’s die architecture, HBM topology, package size, software and IP requirements, qualification schedule, supply geography, and tolerance for process or ecosystem risk. The comparison below separates what each company officially says it can do from what is demonstrated in production or customer products.
What the comparison can—and cannot—prove
Advanced AI chips are manufactured as a system. Leading-edge logic wafers determine compute density and power behavior, but the finished accelerator also depends on HBM memory, interconnects, silicon interposers or bridges, thermal design, assembly, test, and a supply chain that can qualify the complete package. Comparing only a process-node name misses much of the engineering that determines whether a chip can ship.
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How to read process-node names
“2nm,” “3nm,” “18A,” and similar labels are names for a company’s process generation, not universal physical measurements. Different naming conventions can correspond to different transistor dimensions, libraries, interconnect stacks, design rules, and density targets. A 2nm label from one supplier cannot be converted directly into an equivalent transistor density or performance figure for another supplier without comparable product and test data.
For that reason, the useful questions are: Which transistor architecture is used? Is the process in risk production or volume production? Which products have actually used it? What design rules, IP, electronic-design-automation (EDA) flows, and package options are available to the customer?
Side-by-side view
| Comparison axis | Samsung Foundry | TSMC | Intel Foundry |
|---|---|---|---|
| Leading process evidence | SF2 is described as a second-generation MBCFET gate-all-around process for mobile, HPC, AI, and automotive; Samsung also describes its 3nm process as GAA. | TSMC reports 3nm SoIC stacking entering volume production in 2025. Its 2025 annual report schedules N2P and A16 volume production for the second half of 2026. | Intel reported 18A entering production in 2025, using RibbonFET gate-all-around transistors and PowerVia backside power delivery. Core Ultra Series 3 is identified as the first product manufactured on 18A. |
| AI-oriented packaging | Samsung describes qualified, production-available 2.5D packages using a 3.3x silicon interposer and up to eight HBM modules; it also describes CoW 3D packaging and hybrid copper bonding under 6 μm in development. | CoWoS integrates system-on-chip dies and HBM; the portfolio also includes InFO, SoIC, and COUPE for advanced packaging and 3D stacking. | Foveros provides 3D die stacking and EMIB provides silicon-bridge connections. Intel positions these with assembly and test as part of a systems-foundry offering. |
| External-customer evidence | Capabilities and a July 25, 2026 memorandum of understanding with Broadcom are documented. The memorandum is prospective and is not proof of a completed AI-chip production win. | Packaging and process capabilities are documented, but customer-specific qualification, allocation, and lead-time details require customer evidence. | 18A internal product use is documented. Intel says 18A-P remains in development for future Intel products and external foundry customers; this does not establish broad external AI-accelerator production. |
| Comparable public yield, cost, or capacity | Not stated in comparable official material. | Not stated in comparable official material. | Not stated in comparable official material. |
Samsung Foundry: integrated logic, memory, and packaging
Process technology
Samsung’s process documentation identifies SF2 as a second-generation MBCFET (multi-bridge-channel field-effect transistor) gate-all-around process. Samsung lists mobile, high-performance computing, AI, and automotive applications for SF2. Its process materials also describe the company’s 3nm generation as GAA. Gate-all-around devices surround the channel more completely than earlier planar or fin-based structures, giving the designer another way to manage leakage and drive current, but the label alone does not establish a density or yield advantage over a rival’s node.
For a prospective AI-chip customer, the relevant maturity questions are whether the required standard-cell libraries, SRAM options, high-speed I/O, clocks, and third-party IP have completed qualification on the exact SF2 variant, and whether the customer’s package and thermal targets fit the available design rules. Samsung’s public process description establishes intended application coverage; it does not disclose a common, independently measured yield comparison.
2.5D and 3D integration
Samsung’s advanced heterogeneous-integration material describes 2.5D packages built with a silicon interposer that is 3.3 times larger than a stated reference size and says configurations supporting up to eight HBM modules are qualified and available for production. “Qualified and available” is a capability statement; it does not identify a particular accelerator, its shipped volume, or the capacity reserved for a new customer.
Samsung also describes chip-on-wafer (CoW) for 3D packaging and development of hybrid copper bonding with a pitch below 6 μm. CoW and hybrid bonding can reduce vertical interconnect distance and increase bandwidth between stacked dies, but they impose different thermal, assembly, test, and known-good-die requirements than a 2.5D interposer package. A customer must evaluate the complete assembly flow rather than treat these options as interchangeable.
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Customer and partnership evidence
On July 25, 2026, Samsung announced a memorandum of understanding with Broadcom to expand collaboration across memory and foundry technologies. The announcement says the collaboration is expected to extend to advanced packaging built on Samsung’s 2nm process. This is a prospective collaboration: it signals intent and a possible technical path, not a confirmed production design, shipped AI accelerator, or volume allocation.
TSMC: a broad, production-oriented logic-and-packaging portfolio
Process and 3D stacking status
TSMC’s 2025 annual report says 3nm silicon-on-integrated-circuit (SoIC) stacking entered volume production in 2025. That is a dated production statement for the stacking technology, not a claim that every 3nm logic product or every customer package is in volume production.
The same report schedules N2P and A16 volume production for the second half of 2026. A schedule is a forward-looking target; it does not by itself confirm that production started on time or that a particular AI customer has qualified the process. Customers evaluating those nodes should request the current production-readiness milestone, design-rule release, IP qualification list, and package availability directly.
CoWoS and related package technologies
TSMC describes CoWoS as an advanced package for heterogeneous integration of system-on-chip dies and HBM. This approach places multiple compute and memory components on a high-density package substrate or interposer so that the accelerator can obtain much more memory bandwidth than a conventional single-die package.
TSMC’s 2025 annual report also lists InFO, SoIC, and COUPE alongside CoWoS. The portfolio spans fan-out packaging, 3D stacking, and other photonic or chiplet-oriented integration paths. The breadth matters because an AI design may need different combinations of logic dies, cache, I/O, HBM, and optical or electrical links over its lifetime. It does not mean that every named platform offers the same die size, thermal envelope, HBM count, test flow, or lead time.
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The documented production entry for 3nm SoIC is stronger evidence than a future roadmap, while the annual report’s N2P and A16 dates remain schedules. Public descriptions still do not provide a customer-by-customer table of AI accelerators, qualified package configurations, allocated capacity, or delivery lead times. A purchasing decision therefore needs confidential program data in addition to TSMC’s published technology portfolio.
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Intel Foundry: 18A and a “systems foundry” approach
18A process features and production evidence
Intel reported that its 18A process entered production in 2025. The company identifies RibbonFET gate-all-around transistors and PowerVia backside power delivery as core features. RibbonFET uses vertically stacked nanosheet-like channels, while PowerVia moves portions of power delivery to the back side of the wafer; those architectural choices are intended to improve electrical control and routing, but their practical benefit depends on the customer’s design and the qualified implementation.
Intel’s 2025 Form 10-K identifies Core Ultra Series 3 as the first product manufactured on 18A. That demonstrates internal product use on the node. The filing also says Intel continues developing 18A-P for future Intel products and external foundry customers. Development for external customers is not the same as broad, shipped external AI-accelerator adoption, so customers should verify tape-out status, package qualification, and production commitments for their specific program.
Foveros, EMIB, and assembly
Intel’s packaging pages describe Foveros 3D stacking and EMIB silicon-bridge packaging. Foveros connects vertically stacked dies; EMIB uses a bridge embedded in the package substrate to connect adjacent dies. Each method affects die partitioning, thermal paths, assembly yield, test access, and the way HBM or other memory devices are placed.
Intel presents these technologies with process nodes, intellectual property, assembly, and test as a “systems foundry.” That positioning can appeal to a customer that wants one supplier to coordinate more of the manufacturing stack. It remains an Intel characterization, not an independent benchmark of cost, capacity, or customer success. The engineering question is whether the specific combination of 18A or another node, Foveros or EMIB, HBM, substrate, and test services meets the product’s electrical and commercial requirements.
Intel’s market statistic
An Intel Foundry fact sheet states that global manufacturers shipped 1.4 billion AI chips in 2024. This is an Intel-reported figure, not a cross-company market total. The counting definition—what qualifies as an AI chip, which manufacturers are included, and whether products are counted by die, package, or unit—must be obtained before comparing it with another market estimate.
Why packaging and HBM can decide an AI-chip program
Logic is only one part of the accelerator
Large language-model and other AI workloads can be limited by moving data rather than by arithmetic throughput. HBM places wide, high-bandwidth memory stacks close to the compute die. The package must route many signals, distribute power, remove heat, and preserve mechanical reliability while accommodating multiple dies.
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A 2.5D interposer package, a silicon-bridge package, and a 3D bonded stack solve related but different problems. Their die-placement rules, bump or bond pitches, thermal interfaces, test stages, substrate constraints, and known-good-die requirements differ. A claim such as “supports eight HBM modules” should therefore be read as a package capability, not as proof that another supplier’s eight-module package has the same bandwidth, dimensions, thermal design, or production economics.
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- How many HBM stacks are required, and what HBM generation, interface width, and target bandwidth must be qualified?
- What maximum reticle or interposer dimensions and package warpage limits apply to the design?
- Where are thermal sensors, heat spreaders, and liquid- or air-cooling interfaces located?
- Which dies can be tested before assembly, and how are known-good dies screened?
- What package reliability tests, burn-in conditions, and field-replacement assumptions apply?
- What substrate, interposer, HBM, assembly, and final-test capacity is contractually available during ramp?
Design ecosystem: the questions beyond a node name
A foundry’s customer-accessible ecosystem includes process-design kits (PDKs), standard-cell and memory compilers, interface IP, EDA signoff flows, reference designs, and engineering support. It also includes the ability to co-design package, substrate, HBM, and board-level power delivery. The companies’ public materials provide company-level descriptions, but not an equal-depth, independent comparison of PDK release timing, third-party IP coverage, tool interoperability, or support quality.
PDK and IP readiness
Ask for the PDK version tied to the intended tape-out, the list of production-qualified IP blocks, and the change-control policy after design freeze. AI accelerators often require high-speed SerDes, die-to-die links, PCIe or CXL interfaces, large SRAM arrays, clocking, security blocks, and advanced power-management circuitry. An apparently attractive process is not useful if those blocks are unavailable or still undergoing silicon qualification.
Chiplet and package co-design
Determine whether the foundry’s reference flow covers partitioning across compute, I/O, cache, and memory dies; timing and signal-integrity analysis across the package; thermal simulation; and package-aware physical verification. Ask which parts of that flow are supplied directly by the foundry and which must be sourced from an OSAT, substrate vendor, HBM supplier, or EDA provider.
Support and change management
Qualification schedules depend on predictable engineering support. Clarify escalation contacts, model-update frequency, design-rule change windows, mask and reticle revision policy, and the process for handling errata discovered during bring-up. These operational details are often more consequential to schedule risk than a headline node label.
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Customer adoption: separate evidence levels
| Evidence level | What it establishes | What it does not establish |
|---|---|---|
| Company process page | The supplier describes a technology, target applications, or package capability. | Independent yield, a specific customer’s volume, or guaranteed capacity. |
| Roadmap or scheduled date | The company’s planned timing, such as a stated second-half-2026 production target. | That the date was met or that a customer is qualified. |
| Memorandum of understanding | Parties intend to explore or expand collaboration. | A completed tape-out, production win, or shipped product. |
| Internal product in production | The supplier has used the process for its own identified product, such as Core Ultra Series 3 on 18A. | Broad external foundry adoption or equivalent results for another design. |
| Named external product shipping | A customer design has reached a stated production or shipment milestone. | That the same capacity, package, or schedule is available to a new customer. |
Apply this ladder to every announcement. For Samsung, the Broadcom memorandum belongs in the partnership category. For Intel, Core Ultra Series 3 belongs in the internal-product category. For TSMC, 3nm SoIC volume production is a production statement for that technology, while N2P and A16 remain scheduled dates in the cited annual report.
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How to choose a foundry for an AI accelerator
1. Define the package before selecting the process
Start with compute-die count, HBM count and bandwidth, die-to-die links, power envelope, package dimensions, cooling method, and target system density. Eliminate process/package combinations that cannot meet those constraints. A nominally newer logic node is irrelevant if the package cannot route the required memory or dissipate the heat.
2. Build a qualification matrix
| Decision area | Evidence to request |
|---|---|
| Logic process | Production status, PDK release, design-rule revision, SRAM and I/O qualification, and silicon learning data for the exact variant. |
| HBM and package | Supported HBM configurations, interposer or bridge dimensions, thermal limits, assembly flow, reliability results, and package test coverage. |
| Design ecosystem | Qualified IP list, EDA reference flow, chiplet and package co-design tools, and engineering-support commitments. |
| Supply | Fab and assembly locations, allocation policy, ramp assumptions, substrate and HBM dependencies, and contractual lead times. |
| Commercial risk | Mask and NRE assumptions, wafer and package pricing, revision costs, forecast flexibility, and remedies for missed milestones. |
| Customer references | Named products, tape-out dates, production status, and whether evidence is internal, announced, or independently verifiable. |
3. Match the supplier’s strength to the program
- Choose Samsung for investigation when a program benefits from coordinated foundry, memory, and package work, and Samsung’s 2.5D or 3D options match the HBM and thermal design. Confirm the exact SF2 variant, IP readiness, and available package capacity.
- Choose TSMC for investigation when a mature, broad advanced-packaging portfolio and established SoIC or CoWoS paths are central to the design. Confirm the current status of the desired node, customer qualification, and allocation rather than relying on a roadmap date.
- Choose Intel Foundry for investigation when a customer values a vertically coordinated process, package, assembly, and test stack, or needs to evaluate RibbonFET, PowerVia, Foveros, or EMIB. Confirm external-customer readiness and the exact 18A-P or other process milestone.
These are fit-based starting points, not rankings. The same accelerator could reach different conclusions after its HBM topology, software schedule, geography, and volume forecast are known.
Supply, economics, and yield: what is not publicly comparable
None of the cited official materials supplies a like-for-like public comparison of wafer yield, wafer cost, packaged cost, performance per watt, available AI capacity, or customer lead time across all three companies. Yield can vary by die size, design maturity, mask revision, and test definition. Capacity can be reserved by long-term customers and constrained by HBM, substrates, interposers, assembly, or final test rather than by wafer starts alone.
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Cost comparisons also need a common scope. A wafer-only quote excludes masks, engineering runs, package substrate, interposer or bridge, HBM, assembly, test, yield loss, logistics, and qualification. A lower wafer price could still produce a higher delivered cost if package yield or HBM availability is worse. Until suppliers provide comparable definitions and conditions, publishing a numerical “winner” on these measures would be misleading.
A practical due-diligence checklist
- Write the accelerator’s required compute, memory bandwidth, HBM count, power, package size, cooling, and shipment date.
- Request the exact process and package combination, not a generic “2nm,” “3nm,” or “18A” proposal.
- Verify whether each milestone is a roadmap target, risk production, volume production, internal product, named external product, or only a partnership announcement.
- Obtain the PDK revision, qualified IP list, EDA flow, package-design rules, and change-control schedule.
- Ask for capacity commitments covering wafers, HBM, substrates, interposers or bridges, assembly, and final test.
- Model package and HBM thermal behavior and run reliability, burn-in, and known-good-die assumptions through the full system.
- Compare total delivered cost using the same scope and yield definitions for every supplier.
- Secure contractual remedies for schedule slips, allocation changes, and late design-rule or package changes.
Bottom line
TSMC has the clearest publicly documented combination of leading-edge logic and a broad AI-relevant packaging portfolio, including CoWoS and 3nm SoIC production statements. Samsung’s differentiator is the intended integration of foundry, memory, and packaging, with SF2, GAA processes, qualified 2.5D configurations supporting up to eight HBM modules, and developing 3D bonding options. Intel Foundry offers a distinct path built around 18A, RibbonFET, PowerVia, Foveros, EMIB, and a systems-foundry model; its public evidence is strongest for internal 18A product use rather than broad external AI-accelerator adoption.
The right selection is the supplier that can qualify the complete logic-and-package system, provide the required HBM and assembly capacity, support the design flow, and commit to the customer’s schedule. Public company materials are enough to define the candidates and their stated capabilities, but not enough to rank them on yield, economics, capacity, or an overall universal “best” title.
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