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Quantum-chip quality is three different questions, not one score: coherence asks how long a qubit preserves quantum information, fidelity asks how closely a gate, measurement, or prepared state matches its intended result under a stated protocol, and yield asks what fraction of a defined set of fabricated devices passes defined acceptance criteria. Tests are run at cryogenic temperatures and at several stages, from wafer-level structures to packaged processors. Because the metrics use different units, denominators, and protocols, a 95% device yield cannot be compared directly with a 100-microsecond coherence time or a gate-fidelity percentage.
How are quantum chips tested?
Testing begins by defining the device and the question being measured. A laboratory may test an isolated qubit, a gate between two qubits, a readout resonator, a Josephson-junction test structure, a quantum dot, or a complete processor die. The same word—“quality”—can therefore hide very different populations and pass criteria.
Most quantum devices must be cooled well below room temperature so thermal energy does not overwhelm the fragile quantum states. Engineers send microwave, radio-frequency, optical, or voltage pulses to the device, record its response, and repeat the experiment many times to estimate probabilities and error bars. Automated systems then attach each result to a wafer location, die, or qubit identifier. This makes it possible to study both the average device and the tails of the distribution, where unusable or unusually noisy devices appear.
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- Does the qubit stay quantum? Coherence measurements track decay of amplitude or phase while the qubit evolves under controlled conditions.
- Does the operation work as intended? Fidelity measurements compare an implemented state preparation, gate, or readout with its target using a specified characterization protocol.
- How many manufactured devices pass? Yield is the percentage of a stated population meeting a stated threshold. The population might be test structures, qubits, quantum dots, or processor dies.
A result is interpretable only when it names the qubit modality, test conditions, protocol, sample size, and acceptance rule. “A quantum chip is 95% good” is incomplete unless it says 95% of what, tested how, and against which limit.
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Can quantum chips be tested before they are packaged?
Yes. Wafer-level cryogenic probing can characterize many devices before individual dies are cut, wire-bonded, and assembled into a final processor package. A cryogenic prober places electrical contacts on selected structures while the wafer is cooled, allowing screening and statistical measurements without packaging every candidate device.
This approach reduces the cost and time of discarding failed dies late in the process. It also exposes spatial patterns: a cluster of weak devices near one wafer edge can indicate a lithography, deposition, etching, or contact problem that an isolated packaged-chip test would obscure. Pre-packaging tests do not replace all packaged-device measurements. High-fidelity control, crosstalk, calibration drift, and system-level operation may depend on the package, wiring, magnetic shielding, and control electronics.
What wafer-scale demonstrations show
A 2024 Nature study of superconducting transmon fabrication characterized 400 qubits and 12,840 Josephson-junction test structures across 300 mm wafers. The study examined yield, coherence, frequency variation, and aging. Those counts describe that study’s experimental scope; they are not a universal sample size or an industry testing standard.
In a separate company example, Intel described a cryogenic prober operating at 1.7 K on 300 mm silicon wafers. Its October 2022 announcement reported a 95% wafer-wide yield for devices on a particular test chip and said automation characterized more than 900 single quantum dots and more than 400 double quantum dots at the last-electron regime in less than 24 hours. These are Intel-reported results for that program and test-chip context, not an industry-wide benchmark or a yield figure for complete fault-tolerant processors.
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What does coherence mean for a quantum chip?
Coherence is the persistence of usable quantum information. A qubit can lose population, phase information, or both through interactions with its environment. Researchers prepare a known state, allow it to evolve for a controlled interval, and measure how the signal decays. The extracted time constant depends on the experiment, the material, the temperature, the control sequence, and the definition used for the decay.
Free-induction and echo measurements
In a free-induction experiment, often reported as T2*, the qubit evolves without a refocusing pulse. The result includes both rapidly varying noise and slower frequency offsets that differ from run to run. An echo experiment inserts a refocusing operation partway through the evolution. It can cancel some slowly varying errors and therefore often produces a longer T2Echo. Neither number is “the” coherence time; each answers a different question about noise.
A 2024 Nature study of spin-qubit devices reported average free-induction coherence of 0.6 μs in its measured devices and 5 μs for isotopically enriched silicon. Average echo coherence was 98 μs, rising to 205 μs in enriched silicon. The authors identified residual nuclear spins as a limiting factor in those devices. These values are protocol- and device-specific and should not be treated as a direct ranking against superconducting transmons, which use a different physical modality and operating environment.
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How to read a coherence number
- Identify whether the result is T1 (energy relaxation), T2* (free induction), echo coherence, or another metric.
- Check the qubit technology, substrate or isotope, temperature, magnetic environment, and control sequence.
- Look for an average, median, range, or distribution. A high mean can conceal a long tail of poor qubits.
- Check whether the value was measured before or after calibration and whether it changed with aging or repeated thermal cycles.
Long coherence is useful because it gives gates more time to act before information decays, but it does not guarantee accurate control. A device can preserve a state for a long time and still implement a poorly calibrated gate.
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What does fidelity mean for a quantum chip?
Fidelity measures closeness to an intended quantum state or operation. State-preparation-and-measurement (SPAM) fidelity concerns initialization and readout. Gate fidelity concerns the implemented operation, such as a one-qubit rotation or a two-qubit entangling gate. The figure is meaningful only with its scope and protocol: a one-qubit average gate fidelity is not interchangeable with a two-qubit result or a readout percentage.
Why exhaustive process tomography is uncommon
Quantum process tomography reconstructs a detailed model of a channel by preparing many input states and measuring many outputs. The number of experiments grows quickly with the number of qubits, and statistical and calibration errors accumulate. As Dawei Lu and colleagues wrote in a 2015 Physical Review Letters paper, “Full characterization via quantum process tomography is impractical and often unnecessary.”
Scalable alternatives estimate selected properties under explicit assumptions. Randomized benchmarking applies sequences of nominally random Clifford operations, measures the survival probability, and fits its decay as sequence length increases. The result is an average error estimate for the tested gate set under the experiment’s assumptions. It is not a context-free score for every circuit, noise process, or operating point.
Protocol and correction can change the reported result
The 2015 paper illustrates this dependence with a seven-qubit Clifford-gate fidelity study. The experiment used 1,656 experiments for a stated 99% statistical confidence level. The reported fidelity was 55.1%; when signal decay attributable to decoherence was accounted for, the study reported at least 87.5%. This older nuclear-magnetic-resonance processor result demonstrates how the treatment of decoherence changes an estimate; it is not a contemporary manufacturing benchmark.
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A 2021 PRX Quantum study demonstrated a “restless” workflow for randomized-benchmarking measurements on superconducting devices. In the setup studied, single-qubit fidelity measurements were reported as 20 times faster and two-qubit measurements as 8 times faster than the comparison workflow. The speedup describes that method and setup, not a universal throughput guarantee.
Questions to ask about any fidelity claim
- Was the metric for state preparation, readout, a one-qubit gate, or a two-qubit gate?
- Which benchmark was used: randomized benchmarking, process tomography, cross-entropy-style testing, or another protocol?
- Were leakage, measurement errors, drift, or decoherence corrected, and under what model?
- Is the number an average, a worst-case bound, a per-gate estimate, or a distribution over qubits and calibrations?
- How many sequences, repetitions, qubits, and operating points contributed to the estimate?
Fidelity and coherence interact but are not substitutes. A short coherence time can limit the achievable fidelity, while control-pulse imperfections, crosstalk, leakage, and readout errors can reduce fidelity even when coherence is excellent.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How do manufacturers measure quantum-chip yield?
Yield is calculated only after defining a denominator and a pass rule:
Yield = (number of tested items that meet the criterion ÷ number of tested items) × 100%
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“Items” must be named. A wafer study may count Josephson-junction test structures, quantum dots, individual qubits, functioning dies, or complete packaged processors. These denominators cannot be swapped. A high junction-test-structure yield does not establish a high yield of complete processors.
From measurements to a pass/fail rule
- Define the population. Record the wafer, die, qubit, gate, or test-structure count and the sampling plan.
- Define measurable limits. Examples include a frequency window, room for tuning, a minimum coherence value, a maximum leakage rate, or an electrical signature for a quantum dot.
- Run the same protocol. Keep temperature, wiring, pulse settings, calibration method, and measurement duration consistent enough that devices can be compared.
- Classify each item. Mark pass, fail, or indeterminate, and document missing data rather than silently excluding it.
- Map and analyze the distribution. Plot results by wafer position and inspect mean, spread, tails, wafer-to-wafer repeatability, and changes after aging.
Manufacturers often use multiple gates rather than one threshold. A qubit may need acceptable frequency tunability, coherence, readout contrast, and gate performance to count as usable. A die-level pass may additionally require wiring continuity and operation of a minimum number of qubits. Reporting the individual criteria prevents a single aggregate percentage from hiding the reason devices failed.
Uniformity matters alongside the percentage
Two wafers can have the same yield while presenting different engineering problems. One may contain uniformly acceptable devices; another may have excellent devices in one region and a cluster of failures elsewhere. Wafer maps, histograms, and spatial correlation help identify process gradients. Frequency spread, junction resistance variation, coherence distributions, and aging measurements show whether calibration can be shared or must be individualized.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesThroughput is part of manufacturing evidence. A test that measures only a few randomly selected devices cannot establish the same statistical confidence as a broad, automated wafer screen. Conversely, a very large count does not make a weak pass definition meaningful. The report should state how many locations were tested, under what cryogenic conditions, over what elapsed time, and whether the sample represents one wafer or repeated lots.
How to compare quantum-chip test results without being misled
| Comparison axis | What to verify | Why it changes the interpretation |
|---|---|---|
| Qubit modality and device | Spin, transmon, or another architecture; test structure, isolated device, die, or integrated processor | Different physical systems have different noise sources, controls, and failure modes. |
| Coherence protocol | Free induction, echo, relaxation, temperature, material or isotope, and environment | Echo can remove some slow noise, so its value is not interchangeable with free-induction coherence. |
| Fidelity scope | Preparation/readout, one-qubit gate, or two-qubit gate; benchmark and correction assumptions | A percentage without scope does not identify which operation was tested. |
| Yield denominator | Number and type of tested qubits, dots, junction structures, dies, or processors | Percentages from different populations answer different manufacturing questions. |
| Sampling and throughput | Wafer locations, device count, cryogenic conditions, automation, and elapsed time | These determine statistical coverage and practical screening cost. |
| Statistical scope | Average versus distribution, tail behavior, wafer-to-wafer repeatability, and aging | An average can hide outliers or drift that affect usable system size. |
A practical checklist for reading a quantum-chip result
- Write down exactly what was tested and how many items were in the denominator.
- For coherence, record the metric name, pulse sequence, temperature, material or isotope, and device modality.
- For fidelity, identify the operation, benchmark, number of repetitions, and any noise or decoherence correction.
- For yield, find the pass threshold, treatment of indeterminate devices, wafer or lot count, and whether the percentage is company-reported or peer-reviewed.
- Separate pre-packaging screening from packaged-system performance.
- Inspect distributions and wafer maps instead of relying only on a headline average.
- Do not compare a yield percentage with a coherence time or gate-fidelity percentage as though they were competing scores.
The most informative reports connect all three layers without collapsing them: they show whether quantum information survives, whether operations meet a defined error target, and how consistently fabrication produces devices that can reach those targets. A credible result states the modality, conditions, protocol, denominator, threshold, and statistical scope so another laboratory or manufacturer can understand exactly what the number means.
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