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An optical interconnect carries digital data by converting electrical signals into pulses of light, sending those pulses through optical fiber, and converting them back to electrical signals at the destination. Fiber already links switches and servers in data centers; the newer development is placing the optical conversion much closer to an AI or networking chip through near-package optics (NPO), co-packaged optics (CPO), or an optical I/O chiplet. That shorter electrical path can improve bandwidth density and power efficiency, but it also creates difficult packaging, thermal, alignment, manufacturing, service, and standards problems.
How do optical interconnects work?
An optical link is a transport system, not an optical computer. The processors still perform matrix multiplication, memory access, routing, and other computation electronically. Light is used to move the resulting bits between chips, boards, servers, switches, or racks.
1. The source chip creates an electrical signal
A CPU, GPU, switch ASIC, accelerator, or network interface produces a high-speed electrical data stream. Serializer/deserializer circuits (SerDes) arrange parallel data into serial lanes and recover timing. In a conventional system, those lanes travel across a circuit board to a removable optical transceiver. In NPO and CPO designs, the distance to the optical engine is much shorter.
2. An optical engine drives the light
An electronic driver IC feeds a photonic integrated circuit (PIC). A laser supplies the optical carrier, and a modulator changes the light in a controlled way so that the receiver can distinguish ones and zeros. Some designs use several wavelengths on one fiber. Wavelength-division multiplexing (WDM), including dense WDM (DWDM), lets each wavelength carry an independent channel while the channels share the same physical fiber.
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3. Fiber guides the signal
Single-mode fiber confines the light to one propagation mode and is the normal medium for long-reach, high-capacity data-center links. The fiber may run from a faceplate transceiver to another rack, from an external laser module to a co-packaged optical engine, or between optical I/O chiplets and a remote system. Connectors, fiber-array units, bends, cleanliness, and alignment all affect insertion loss and reliability.
4. The receiver converts light back to electricity
At the destination, a photodetector turns the modulated light into a small electrical signal. Transimpedance amplifiers and other receiver electronics condition it; clock and data recovery restores timing; and the destination chip receives electrical lanes in its expected protocol and voltage range. Forward-error correction may be used by the link protocol to tolerate a defined error rate, but it does not remove the need for good optical power budgets and precise assembly.
How do AI chips communicate in a data center?
AI systems use several communication scales at once. Inside a package, short electrical connections link compute tiles, cache, and memory interfaces. Between packages on one accelerator board, copper traces and connectors remain practical for short distances. Between servers, top-of-rack switches and network adapters commonly use pluggable optical transceivers. Between racks or across a data hall, fiber provides the reach and bandwidth density that copper cabling generally cannot provide at the same signaling rates.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsThe architectural change called optical I/O moves the electrical-to-optical boundary toward the compute package. A GPU or CPU can therefore present a high-bandwidth optical interface without sending every high-speed electrical lane across a long board trace to the front panel. The optical link still terminates in a network, fabric, or peer accelerator; it does not make the computation itself photonic.
In a conventional switch, the ASIC is deep inside the chassis, the electrical lanes cross the board, and the transceiver is plugged into the faceplate. Corning describes an illustrative path with about a foot of copper traces between the chip and the faceplate module; that is an example architecture rather than a universal measurement. NPO places the engine near the package while retaining some physical separation. CPO integrates the optical engine in the same package as the ASIC or compute silicon.
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Why use fiber instead of copper in AI data centers?
Copper remains valuable for short links because it is familiar, easy to terminate, and comparatively simple to replace. As signaling rates rise, however, electrical loss, distortion, crosstalk, and the power required for equalization become more consequential. Fiber avoids many of those distance-related electrical impairments and can carry multiple high-speed wavelengths through a small cable.
| Decision factor | What fiber can offer | What engineers must still account for |
|---|---|---|
| Reach | Longer links than many passive electrical connections, including inter-rack and inter-row runs | Optical power budget, connector loss, bends, and the protocol’s specified reach |
| Bandwidth density | Several lanes or wavelengths can share a fiber assembly | Laser count, modulator speed, fiber count, and connector density |
| Power | Shorter electrical paths can reduce the energy spent driving and equalizing copper | Lasers, drivers, cooling, conversion electronics, and control circuits consume power |
| Latency | Removing long electrical routes can simplify signal paths | Propagation in fiber, optical conversion, buffering, protocol overhead, and distance still determine end-to-end latency |
| Operations | Fiber is immune to electromagnetic interference and supports high-density cabling | Cleaning, inspection, bend protection, polarity, labeling, and specialized repair skills |
| Economics | Potentially lower energy per transported bit at very high bandwidth | Photonics packaging, yield, test equipment, spares, and ecosystem maturity affect total cost |
There is no universal rule that an optical link is always cheaper, cooler, or faster. A fair comparison measures the complete port or system, including conversion electronics, cooling, cabling, switch capacity, distance, and maintenance.
What is co-packaged optics?
| Architecture | Where conversion occurs | Main benefit | Main engineering trade-offs |
|---|---|---|---|
| Pluggable optics | Removable transceiver at the equipment faceplate | Familiar module boundary, field replacement, and straightforward fiber access | Longer electrical traces from the ASIC to the module; module power, front-panel density, and signal conditioning become limiting factors |
| Near-package optics (NPO) | Optical engine near the ASIC or package | Shorter electrical path without putting every optical component inside the main package | Fiber routing, packaging, service access, and mechanical integration remain difficult |
| Co-packaged optics (CPO) | Optical engine in the same package as the ASIC or compute silicon | Very short electrical path and potentially dense optical I/O | Shared thermal environment, fiber attachment and alignment, manufacturing yield, repair strategy, and standards |
| Compute optical I/O chiplet | A separately fabricated optical I/O subsystem co-packaged with a CPU, GPU, IPU, or SoC | Extends optical connectivity closer to compute and could enable new system layouts | Many announced designs are demonstrations or roadmaps rather than broadly deployed accelerator products |
The 2026 Nature Electronics review discusses two-dimensional CPO, 2.5-dimensional interposer integration, and three-dimensional heterogeneous stacking. These approaches differ in how optical engines, electronic dies, interposers, and fiber attach are arranged. The choice affects thermal paths, assembly tolerances, test coverage, and whether a failed component can be replaced independently.
What has been demonstrated?
Intel’s OCI demonstration
At OFC 2024, Intel reported a live CPU-co-packaged optical I/O demonstration. Intel specified 64 channels operating at 32 Gbps in each direction, up to 100 meters over single-mode fiber, and eight fiber pairs with eight DWDM wavelengths per fiber pair. The resulting capacity was reported as 4 Tbps bidirectional. Intel also reported 5 picojoules per bit for that co-packaged demonstration, compared with about 15 pJ/bit for pluggable optical transceiver modules.
Those figures belong to Intel’s particular demonstration and comparison method. They are not an industry-wide guarantee that every CPO implementation uses 5 pJ/bit or that optical links consume one-third the power of copper. Intel noted that practical applications may be limited to tens of meters when time-of-flight latency matters, even though the demonstration reached up to 100 meters.
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Intel’s product information describes a first-generation OCI chiplet supporting 4 Tbps bidirectionally over standard single-mode fiber and designed for co-packaging with next-generation CPUs, GPUs, IPUs, and other SoCs. The same company reports that its silicon-photonics platform has shipped more than 8 million PICs containing more than 32 million on-chip lasers embedded in pluggable optical transceivers. That shipment total measures the established pluggable platform; it does not mean that millions of compute optical I/O chiplets have shipped.
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NVIDIA’s announced photonics switches
In an announcement dated March 18, 2025, NVIDIA described Spectrum-X Photonics Ethernet and Quantum-X Photonics InfiniBand switches using CPO. The announcement gave a later-2025 expectation for Quantum-X Photonics switches and a 2026 expectation for Spectrum-X Photonics Ethernet switches. A product page available in 2026 lists up to 409.6 Tb/s of bandwidth and second-half-2026 availability for Spectrum-X Ethernet Photonics.
These are vendor-stated specifications and schedules. An availability target, an announced design, and an installed production fleet are different evidence levels. Buyers should confirm the shipping configuration, supported optics, software version, warranty terms, and deployment references before treating a target date as an operational capability.
What makes optical I/O difficult to deploy?
Thermal design
Electronic drivers, lasers, modulators, detectors, and switch silicon can share a constrained package or enclosure. Their allowable operating temperatures may differ, while the ASIC itself can be one of the largest heat sources in the system. Cooling must preserve optical performance and laser lifetime without reducing compute density. A design that saves electrical power at the interface can still require substantial cooling hardware.
Manufacturing yield and test
CPO combines high-value electronic dies, photonic dies, package substrates, fiber attachments, and optical alignment in one assembly. Each additional connection creates an opportunity for loss, contamination, or failure. Manufacturers need wafer-level and package-level tests that identify defects before a complete switch or accelerator is assembled. Low yield can erase the expected cost and energy benefits.
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Fiber routing and alignment
Many fibers must leave a small package without violating bend radius, polarity, or strain limits. Fiber-array units and compact connectors need repeatable alignment measured in micrometers. Routing also has to survive vibration, thermal cycling, installation, and maintenance. Dust on a connector end face can cause enough loss to destabilize a high-speed link.
Serviceability
A failed pluggable transceiver can normally be removed without replacing the switch ASIC. A co-packaged optical engine may be inseparable from the package, making a repair more like a board or system replacement. One alternative is an external light-source module: Ciena’s CPO/NPO Vesta architecture describes replaceable external sources that can be serviced on-site. That approach preserves some service flexibility but adds fiber and module interfaces that must themselves be managed.
Standards and interoperability
Optical engines, connectors, electrical interfaces, management telemetry, and software controls may be specific to a platform. The existence of one vendor’s CPO engine does not prove that it can be exchanged with another vendor’s engine or connected to every switch ASIC. The 2026 review identifies standardization as an unresolved issue, so procurement teams should request interoperability matrices rather than assume a common connector guarantees system compatibility.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How should bandwidth, power, and latency claims be interpreted?
Bandwidth can be stated per lane, per direction, per fiber pair, per port, or for an entire switch. Intel’s 4 Tbps figure is bidirectional capacity in a specific OCI demonstration; it is not 4 Tbps of application payload after protocol overhead in every deployment. NVIDIA’s 409.6 Tb/s figure is a vendor-listed switch bandwidth ceiling, not a measurement of an individual optical cable.
Energy figures also need their boundary defined. Intel’s 5 pJ/bit versus approximately 15 pJ/bit comparison refers to its co-packaged demonstration and pluggable optical transceiver modules. It does not establish a cross-vendor result for complete racks, including cooling, switch fabrics, lasers, and host processors.
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Latency includes serialization, electronic and optical conversion, propagation, buffering, switching, and any error-recovery mechanism. Fiber propagation is fast but not instantaneous, and a longer optical path can add measurable time-of-flight delay. Moving a transceiver next to an ASIC may reduce an electrical route while adding optical conversion; only an end-to-end measurement under the intended protocol answers whether the system is faster.
How mature is the technology?
| Evidence type | What it establishes | What it does not establish |
|---|---|---|
| Laboratory or conference demonstration | Specified components worked under the demonstrated conditions | Volume manufacturing, long-term reliability, or field service at scale |
| Vendor product announcement | A company has described an architecture, partner ecosystem, or intended product | That the product is shipping, interoperable, or deployed widely |
| Published availability target | The vendor’s planned timing at the stated date | Actual delivery dates, final specifications, or customer acceptance |
| Shipment statistic | A stated number of a defined component or platform has shipped | Shipment of a newer component with a similar name or architecture |
| Production deployment reference | Evidence that a defined configuration operates in a real environment | Performance or economics in every workload and data-center design |
For example, Intel’s millions of PICs and lasers refer to pluggable transceivers, while its OCI chiplet is a newer co-packaged design. Keeping those categories separate prevents a mature manufacturing record from being mistaken for proof of mass deployment of compute optical I/O.
What should an engineering team check before choosing CPO or NPO?
- Define the traffic pattern. Record port count, lane rate, directionality, oversubscription, message size, synchronization requirements, and whether traffic stays within a rack or crosses a data hall.
- Set a complete link budget. Include fiber length, connector count, splice loss, wavelength plan, temperature range, receiver sensitivity, and allowance for aging and contamination.
- Measure the whole-system power boundary. Ask whether quoted pJ/bit includes lasers, drivers, thermal management, retimers, management controllers, and cooling.
- Validate latency at the application interface. Measure serialization, conversion, propagation, switch buffering, and software behavior rather than relying on a headline optical data rate.
- Plan replacement procedures. Determine whether an optical engine, laser source, fiber assembly, or complete board is replaceable in the field, and stock the appropriate spares.
- Qualify manufacturing and reliability. Request temperature-cycle, vibration, fiber-attachment, connector-mating, burn-in, and failure-analysis data appropriate to the deployment.
- Confirm interoperability. Check electrical standards, optical wavelengths, management protocols, firmware support, connector type, and the exact switch or accelerator revision.
- Separate committed products from roadmaps. Obtain a purchaseable part number, shipping date, support policy, and deployment references before designing a production cluster around a target.
Where does this leave optical interconnects?
Fiber is already a normal part of data-center networking. The significant shift is not the invention of fiber links, but the relocation of optical conversion from a removable front-panel module toward the ASIC or compute package. That shift can address electrical loss and power at extreme bandwidths, especially when many AI accelerators must exchange data continuously.
CPO, NPO, and compute optical I/O are therefore system architectures rather than drop-in cable upgrades. Their value depends on the workload’s distance, bandwidth, latency budget, thermal envelope, maintenance model, and manufacturing scale. Demonstrations from Intel and announcements from NVIDIA show credible progress, while the unresolved packaging, service, standards, and deployment questions determine when a particular design is ready for production.
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