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PCIe 6.0 specifies eight times the per-lane transfer rate of PCIe 3.0: 64.0 GT/s versus 8.0 GT/s. It reaches that rate with PAM4 signaling and adds fixed-size Flit-mode transfers, forward error correction (FEC), and CRC. Those are interface specifications, not a promise that an application or device will run eight times faster.
How do PCIe 3.0 and PCIe 6.0 compare?
The figures below describe the standards, not measured application performance. Per-lane rates are in GT/s; x16 bandwidth is shown in the units and form PCI-SIG reports. PCI-SIG’s 2024 presentation lists the generation rates, encoding, and encoding-adjusted x16 bandwidth for generations 3.0 through 6.0. Its separate overview describes PCIe 6.0 x16 bandwidth as bidirectional.
| Generation | Release year listed by PCI-SIG | Rate per lane | Encoding or signaling | x16 bandwidth |
|---|---|---|---|---|
| PCIe 3.0 | 2010 | 8.0 GT/s | 128b/130b encoding | 126 Gb/s after encoding overhead |
| PCIe 4.0 | 2017 | 16.0 GT/s | 128b/130b encoding | 252 Gb/s after encoding overhead |
| PCIe 5.0 | 2019 | 32.0 GT/s | 128b/130b encoding | 504 Gb/s after encoding overhead |
| PCIe 6.0 | 2022 | 64.0 GT/s | PAM4 signaling with Flit mode, FEC, and CRC | 1,024 Gb/s after encoding overhead; up to 256 GB/s bidirectional |
Generation-table values are from PCI-SIG’s 2024 presentation; the PCIe 6.0 bidirectional x16 figure is from its specification overview. Gb/s means gigabits per second, while GB/s means gigabytes per second. PCI-SIG describes 256 GB/s as total bidirectional bandwidth for x16, not 256 GB/s in each direction. These x16 figures assume a sixteen-lane link; a narrower link carries less bandwidth.
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PAM4 raises the transfer rate
PCIe 3.0 uses 128b/130b encoding at 8.0 GT/s per lane. PCIe 6.0 uses four-level pulse-amplitude modulation (PAM4), which encodes two bits per signaling interval. PCI-SIG says it retains a 16 GHz Nyquist frequency while reaching 64.0 GT/s. This is why the headline rate increases without simply raising the signaling frequency by the same factor.
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FEC and CRC address signaling errors
PAM4 has a higher bit error rate than the signaling approach used by earlier generations. PCIe 6.0 uses lightweight forward error correction (FEC) and cyclic redundancy check (CRC) to mitigate that increased error risk. These mechanisms are part of the link’s reliability approach; they do not turn the transfer rate into guaranteed application throughput.
Flit mode changes how data is packaged
PCIe 6.0 introduces Flit mode, which exchanges fixed-size 256-byte Flits containing variable-sized transaction-layer packets (TLPs) and data-link-layer payloads (DLLPs). PCI-SIG’s FAQ says fixed-size Flits are needed alongside PAM4 and FEC. Flit mode is supported at all link speeds, not only at 64 GT/s; translation takes place at boundaries between Flit and non-Flit links. See the PCI-SIG PCIe 6.0 FAQ.
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Will PCIe 6.0 work with PCIe 3.0?
PCI-SIG states: “Yes, PCIe 6.0 products will interoperate and maintain backwards compatibility with all previous generations of PCI Express technology.” This is a standards-level interoperability statement, not a guarantee that a particular component will work in every system or operate at PCIe 6.0’s maximum rate.
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What does the difference mean for performance?
At the specification level, PCIe 6.0’s 64.0 GT/s per lane is eight times PCIe 3.0’s 8.0 GT/s, with each intervening generation doubling the rate. Actual application performance is a separate question: it depends on the device, host, negotiated generation and lane width, and the workload. The interface rate alone cannot establish a universal speedup, and the cited specifications do not provide application benchmark results.
PCI-SIG’s presentation lists PCIe 3.0 as released in 2010, PCIe 4.0 in 2017, PCIe 5.0 in 2019, and PCIe 6.0 in 2022. Those dates describe the presentation’s generation table, not the availability of a specific product or its support in an individual computer.
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