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Hardware makers are adding post-quantum cryptography (PQC) to secure controllers, cryptographic accelerators, and microcontroller platforms. The capabilities they describe include secure boot, firmware-update verification, attestation, and certificate handling. These are product announcements, not independent proof of deployment or performance; choosing a platform still requires checking its algorithms, integration, resource needs, and interoperability.
What does post-quantum cryptography mean for hardware?
PQC refers to cryptographic algorithms designed to resist attacks from future quantum computers. It does not mean that current quantum computers can already break deployed public-key cryptography. The hardware work is part of a broader transition involving devices, software, services, and communications protocols.
NIST published three principal PQC standards on August 13, 2024: FIPS 203, the Module-Lattice-Based Key-Encapsulation Mechanism (ML-KEM); FIPS 204, the Module-Lattice-Based Digital Signature Algorithm (ML-DSA); and FIPS 205, the Stateless Hash-Based Digital Signature Standard (SLH-DSA). ML-KEM is for establishing shared keys; ML-DSA and SLH-DSA are signature standards, not encryption algorithms. NIST’s PQC standardization page lists the standards.
How are hardware makers implementing post-quantum cryptography?
Implementations can put PQC operations in a secure controller or hardware root of trust, accelerate them in dedicated cryptographic hardware, or provide software libraries that run on general-purpose or secure microcontrollers. Product descriptions also place these operations inside device-security workflows: verifying boot code and firmware updates, authenticating devices, producing attestations, and handling certificates.
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Secure controllers and roots of trust
In an April 28, 2026 announcement, Microchip described the TS1800 as an external platform root-of-trust controller for secure boot, secure firmware updates, attestation, and certificate handling. The company said it includes hardware-accelerated ML-DSA, LMS signature verification, and ML-KEM. These are capabilities Microchip describes; the announcement is not an independent validation or deployment report. Microchip’s TS1800 and TS50x announcement.
Embedded controllers
In a May 15, 2025 announcement, Microchip described its MEC175xB embedded controllers as having immutable PQC support, with configurable secure boot and firmware-update signature verification. The announcement does not by itself establish measured performance or broad product deployment. Microchip’s MEC175xB announcement.
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Accelerators and software libraries
STMicroelectronics described hardware cryptographic accelerators and associated software libraries for general-purpose and secure microcontrollers, aimed at firmware updates, secure boot, and authentication. The announcement does not identify a part number in the available description, so a specific model should not be inferred. STMicroelectronics’ 2025 announcement.
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Hardware security modules (HSMs), trusted platform modules (TPMs), secure controllers, and other cryptographic modules may need upgrades or redesign. NIST’s IR 8547 initial public draft, published November 12, 2024, notes that larger keys and higher computational demand can affect implementation, and highlights optimization and side-channel protection as engineering considerations. NIST states: “Hardware modules must be upgraded or redesigned to support PQC algorithms, which often have larger key sizes and require more computational resources.” This is draft transition guidance, not final policy. NIST IR 8547.
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The practical impact depends on where a device uses public-key cryptography and how its security functions are implemented. A controller that verifies a signature during boot has different constraints from a device that frequently establishes keys or handles certificates. Memory, bandwidth, compute capacity, power budget, and resistance to side-channel attacks all matter; a product label alone does not show how well those needs are met.
How should an organization plan the hardware transition?
Start with cryptographic visibility, not a product shortlist. NIST’s National Cybersecurity Center of Excellence migration project frames the work as finding where vulnerable public-key cryptography is used across hardware, software, and services, then managing risk and prioritizing migration. Its work also addresses interoperability and benchmarking. NIST NCCoE’s PQC migration project.
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- Inventory cryptographic use. Identify devices, modules, software, services, protocols, keys, certificates, and dependencies that rely on public-key cryptography.
- Map each use to its security function. Determine whether cryptography is used for boot verification, update signing, authentication, attestation, or key establishment, and where the operation runs.
- Separate updateable systems from redesign candidates. Check whether firmware or libraries can be upgraded, whether the hardware has sufficient resources, and whether its trust anchor can support the required algorithms.
- Test the full system path. Confirm that device, certificate, protocol, and service changes work together. Hardware support alone cannot complete a migration when other system components remain incompatible.
What should you compare in a PQC-ready hardware platform?
Compare documented capabilities against the actual security functions and lifecycle of the product. “PQC-ready” is not, by itself, evidence of a particular certification, interoperability, or measured performance.
| Comparison area | Questions to ask |
|---|---|
| Algorithm coverage | Which standardized algorithms are implemented? Is support for hybrid operation documented where it is relevant to the migration? |
| Implementation location | Are operations hardware accelerated, handled by firmware or software libraries, or split between these approaches? |
| Trust anchor | Does trust reside in a discrete secure controller, a TPM or HSM, or a general-purpose microcontroller platform? |
| Security integration | Does the platform support the specific needs for secure boot, update verification, attestation, authentication, and key or certificate handling? |
| Resource and security evidence | What memory, bandwidth, compute, and power measurements are available, and under what conditions? What evidence covers side-channel protections? |
| Migration and interoperability | What migration path, crypto-agility, interoperability testing, and validation status are documented? |
Ask vendors for measurements taken under comparable conditions before drawing conclusions about speed or power. The cited standards, migration guidance, and announcements do not establish a controlled cross-vendor performance ranking, a broad adoption rate, or independent validation of the announced products.
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