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Chipmakers adopt a new lithography process when it can reliably make the patterns a product needs and the gains justify changing the entire manufacturing flow—not simply because a process node has a newer name. They weigh resolution and chip performance against yield, defects, throughput, cost, design migration, customer demand and the readiness of materials and suppliers. Adoption can begin on selected layers or products, while older techniques remain in use elsewhere.
What decision are chipmakers actually making?
Lithography transfers patterns onto a wafer. Those patterns define structures in the chip, so the process affects which features can be manufactured and how reliably they can be repeated. A new lithography method may enable finer patterning, greater density, or a more efficient way to build a product. But a scanner does not operate in isolation: its output must fit into a sequence of deposition, lithography, etch, planarization, inspection and other steps.
That is why adoption is a manufacturing decision about an integrated process, not a simple equipment purchase. A company needs evidence that the technique works on the intended layers, meets production requirements, and improves the economics or product capability enough to offset equipment, integration, qualification and design costs. The sources do not establish one universal yield cutoff, return-on-investment equation or break-even point; those depend on a company’s process, products and manufacturing plans.
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Nor does a node label answer the question. ASML describes node names as generation labels; a label alone does not specify which lithography tools or patterning strategy a manufacturer should use. The relevant question is what the process enables for a given product and whether the complete flow can deliver it at production scale.
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How do chipmakers evaluate a proposed process?
1. Identify a product need and the patterns required
The starting point is the target device and its manufacturing requirements. Engineers ask whether the proposed technique can print the desired features and structures on the layers where they matter. They consider resolution and critical dimensions—the sizes of features that must be formed—as well as pattern fidelity, or how accurately the printed pattern matches its intended design.
EUV lithography, for example, is used for the most intricate chip layers, while deep ultraviolet (DUV) lithography remains in use for other layers. ASML expects the two technologies to coexist for years. A manufacturer therefore does not necessarily replace one technology everywhere when it introduces another. A higher-resolution technique such as High-NA EUV may be useful for a subset of demanding layers, while other layers continue to use established approaches.
2. Prove that the integrated process is controllable
Printing a pattern once is not enough. A manufacturing process must repeat it across wafers and over time, with acceptable critical-dimension variation, overlay, defectivity and stability. Overlay is the accuracy with which a new pattern aligns to patterns already present on the wafer. Misalignment or defects can make otherwise usable chips fail.
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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11TSMC’s 2024 annual report describes lithography work for 2nm risk production that included improving wafer yield, EUV scanner application efficiency, material defects, planarization and overlay. These are examples of the interdependent issues a manufacturer has to control: the scanner’s performance matters, but so do the materials and surrounding steps that determine whether the printed pattern survives the full process.
Imec describes evaluating High-NA patterning for resolution, defectivity, critical-dimension stability and depth of focus. High-NA’s larger numerical aperture improves resolution, but it reduces depth of focus compared with 0.33-NA EUV. That tighter focus range makes process adjustments important; one example Imec identifies is using thinner resist films. Better nominal resolution, by itself, does not establish that a process is ready.
3. Compare complete flows, not isolated exposures
The meaningful comparison may be between two ways of making the same set of features. An established approach might require multiple exposures and related processing steps to create a pattern. A newer technique could allow some critical layers to return from multi-patterning to single patterning. Imec says High-NA could do this for some layers, potentially relieving cost, yield risk and cycle time. ASML also notes that fewer steps in high-volume production can reduce defects, cost and cycle time.
Those are potential benefits, not automatic savings. Imec notes that multiple EUV exposures will still be needed as pitch scaling continues, and that they add process cost and complexity. A fair comparison accounts for the whole flow: exposure and mask counts, process steps, materials, equipment, inspection and the number of usable dies produced. Fewer exposures could simplify manufacturing, but the new process must first meet production expectations for defectivity, overlay, yield, stability and throughput.
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →The comparison also includes the costs of bringing the new method into the factory: equipment, process integration, materials, masks, training and qualification. The cited industry material explains these dimensions but does not give a universal equipment-price break-even or numerical yield hurdle. A precise financial threshold should not be inferred from the technology examples alone.
4. Account for customer designs and product mix
A process transition can demand design work as well as factory work. Customers may need to adapt layouts, validate intellectual property (IP), use updated design rules or models, and repeat some design and tape-out steps. A process with attractive manufacturing characteristics may be harder to adopt if customers cannot migrate their designs economically or on the needed schedule.
TSMC’s N6 illustrates one way to reduce that friction. TSMC says N6 adds EUV layers while retaining backward-compatible design rules, device models, IP and electronic design automation (EDA) tool availability with N7. It says N7 customers can sustain their design investments as they move to N6. For re-tape-outs, TSMC attributes yield improvement to fewer masks and a simpler process. This is a particular compatibility example, not a promise that every process transition preserves existing designs.
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The product’s market matters too. TSMC lists applications for its N7 platform across smartphones, high-performance computing (HPC), automotive, consumer electronics, networking and other sectors. Different products can value density, performance, power consumption, cost and qualification schedules differently. A process improvement that matters greatly to one product may not justify a migration for another.
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TSMC’s technology page gives one concrete, qualified comparison: for N7 versus N16, it states a 30% speed improvement, 55% power saving and three times the logic density. Those are TSMC’s stated figures against the N16 baseline; they are not general predictions for other node transitions or proof that every product receives the same outcome.
5. Confirm that the supporting ecosystem is ready
A scanner is only one part of a usable lithography process. The ecosystem includes photomasks, resist and underlayer materials, metrology, imaging, optical proximity correction (OPC), etch, wafer handling and suppliers able to provide consistent production support. If one part cannot meet the required specifications or volume, production may be constrained even when the scanner can print the pattern.
Imec describes shared High-NA preparation across materials, photomasks, metrology, imaging, OPC, and integrated patterning and etch. Its High-NA lab is intended to help foundries and integrated device manufacturers de-risk the technology and develop use cases before scanners are operational in production fabs. That preparation addresses a practical adoption question: can the full chain of process steps and supporting technologies work together, not merely demonstrate a promising image?
Mask infrastructure is one specific example. In a September 8, 2026 announcement, ASML and TSMC described an initiative to develop a larger photomask format for High-NA. Their announcement says High-NA production will begin using current six-inch masks, with a later move to twelve-inch masks expected to improve productivity, lower costs and remove stitching constraints. Those are expected benefits of an announced initiative, not evidence that the larger format has already become an industry-wide production standard.
What makes a new lithography process ready for production?
“Ready” is not a single scanner milestone. A proposed process has to work at the intersection of patterning capability, repeatability, production performance and operational support. In practice, manufacturers compare the current and proposed flows across several dimensions:
| Decision area | Questions to answer |
|---|---|
| Patterning capability | Can it print the required resolution, critical dimensions and structures, with adequate pattern fidelity and overlay? |
| Process performance | Are yield, defectivity, stability, throughput, availability and cycle time acceptable in the integrated flow? |
| Flow complexity and economics | How do exposure and mask counts, added steps, equipment and materials affect cost per usable die and production time? |
| Design migration | Can customers reuse design rules, IP, models and EDA tools, or will a transition require substantial redesign and requalification? |
| Ecosystem readiness | Are masks, resists, metrology, OPC, etch, handling and supplier capabilities ready to support production? |
| Product and customer fit | Do the process benefits matter to the intended products, and is demand sufficient to justify capacity and qualification? |
The criteria interact. For example, a process might offer useful resolution but require additional adjustments to resist, focus control or etch. A flow with fewer patterning steps might reduce complexity, but only if yield and throughput remain suitable. Design compatibility might make customer migration easier, but the factory still has to qualify the manufacturing process. Adoption is the decision that the combined case is strong enough for a particular use—not a judgment based on one attractive metric.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why does a new process take years to reach high-volume manufacturing?
A new lithography method has to move from capability demonstration to an integrated, controllable flow and then to sustained production. Work on masks, materials, inspection and process integration can proceed alongside scanner development, but those pieces must ultimately meet production needs together. Manufacturers also need to qualify the intended layers and products, prepare design support, train teams and make sure suppliers can support the required process.
Qualification work can happen in shared labs before production-fab deployment. Imec’s March 18, 2026 release described installing an EXE:5200 High-NA EUV system in its 300mm cleanroom in Leuven to develop industry-scale patterning and next-generation use cases. It said qualification was expected by Q4 2026. That was a dated expectation in the release; it should not be read as confirmation that qualification subsequently occurred.
Even after a process enters production, expansion can remain selective. A manufacturer may qualify it on certain layers or for certain products first, rather than converting all layers or product families at once. The reasons follow from the decision itself: each use must justify its process, design and supply-chain requirements.
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What does High-NA EUV’s reported use at Intel show?
A September 7, 2026 statement from Intel Foundry and ASML reported High-NA EUV use in high-volume manufacturing at Intel Foundry, including selected layers for a subset of Intel Core Ultra Series 3 processors made on Intel 18A. The companies said overlay, throughput and availability were meeting Intel Foundry’s expectations, and that customers could use the existing six-inch mask format with floor-planning or stitching approaches.
The companies also reported more than one million wafers processed across certification, testing, research and development, and volume production. That combined figure covers multiple activities; it is not a claim that one million wafers were produced in high-volume manufacturing. The announcement is a company-reported example of deployment at a defined scope. It does not establish that High-NA has been adopted across all Intel layers or products, or that other manufacturers have adopted it on the same schedule.
The example makes an important distinction: a technology can reach production use without becoming the default method everywhere. The reported use was for selected layers and a subset of products. Broader adoption remains specific to each company’s process plans, product requirements and readiness.
Is there a simple rule for when to switch?
No universal rule is established by the cited material. It provides decision dimensions and examples, not a fixed yield threshold, financial formula or date at which every chipmaker should adopt a process. A sensible decision asks whether the proposed flow can print the target patterns reliably, improve outcomes that matter to the product, and justify its full manufacturing and migration costs.
That is why the same lithography advance can be worthwhile for one layer or product and not yet for another. The evaluation is not simply “new node versus old node”; it is a comparison of achievable product results, manufacturing readiness and customer economics for a defined use.
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