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ASML chipmaking scanners project a circuit pattern from a reticle onto a wafer coated with photoresist. The wafer is developed, etched or otherwise processed, coated again, and exposed repeatedly. EUV scanners use 13.5 nm light for the smallest, most demanding layers; DUV scanners use 193 nm, 248 nm, or 365 nm light for most other layers.

Both technologies are needed because a modern chip is not printed in one exposure. Manufacturers choose the least complex scanner that can meet each layer’s resolution, alignment, and cost requirements. EUV provides the shortest wavelength, while DUV remains the workhorse for the majority of layers.

What an ASML lithography machine actually does

A lithography scanner is a precision projection system, not a device that carves a finished circuit directly into silicon. A reticle, also called a mask, carries the pattern for one chip layer. The scanner illuminates that reticle, reduces its image through an optical system, and focuses the reduced pattern onto photoresist on a silicon wafer.

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After exposure, the wafer goes through chemical development so selected parts of the resist remain or are removed. Etching, deposition, implantation, cleaning, and inspection then transfer or modify the pattern in the underlying materials. The wafer is coated with fresh resist and exposed again for the next layer. A finished processor or memory device therefore results from many tightly aligned lithography cycles.

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ASML describes the process as projecting a blueprint onto the wafer. Different feature sizes require different lithography systems, which is why a fab operates several scanner types rather than relying on a single machine.

How one exposure moves from reticle to wafer

  1. Prepare the wafer. A silicon wafer receives a thin photoresist coating. The resist is sensitive to the scanner’s wavelength and is engineered for the process layer being printed.
  2. Load the reticle. The reticle contains the geometric pattern for that layer. It is positioned and held with the accuracy required for repeating the pattern across many wafer fields.
  3. Generate and shape the light. DUV tools use excimer-laser sources or mercury sources. EUV tools generate 13.5 nm radiation and condition it into a usable exposure beam.
  4. Illuminate the pattern. The optical system directs light onto the reticle. The reticle is larger than the image printed on the wafer, so the projection optics reduce the pattern.
  5. Project and focus. The scanner forms a reduced image on the resist. Wavelength and numerical aperture (NA) determine how finely the system can resolve neighboring features.
  6. Align the layer. The wafer stage positions each field and aligns it to patterns already present on the wafer. This layer-to-layer registration is called overlay.
  7. Expose the fields. A step-and-scan motion exposes one field, moves the wafer, and repeats until the usable wafer area is covered.
  8. Develop and process. Development reveals the intended resist image. Etch or other process steps transfer that image, after which the surface is cleaned and prepared for the next cycle.

The scanner performs the exposure and alignment part of this chain. It does not replace the deposition, etch, metrology, cleaning, or inspection equipment surrounding it in a semiconductor fab.

What makes EUV different

13.5 nm light

EUV uses a 13.5 nm wavelength, close to the X-ray region. That wavelength is far shorter than the 193 nm light used by advanced ArF DUV systems, so it can resolve much smaller features under comparable optical conditions. ASML’s product description characterizes 13.5 nm as almost X-ray range.

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Vacuum instead of air

Air absorbs EUV strongly, and ordinary glass or other conventional lens materials cannot transmit it. The source, reticle, projection path, and wafer exposure region therefore operate in high vacuum. Removing air is not an optional cleanliness measure; it is necessary for the light to reach the wafer.

Mirrors instead of lenses

Because transmissive lenses do not work at 13.5 nm, EUV scanners use all-reflective optics. Specialized multilayer mirror coatings reflect the wavelength, and a sequence of mirrors guides, reduces, and focuses the reticle image. Every reflection introduces demanding requirements for surface quality, coating uniformity, contamination control, and alignment.

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A system-level engineering challenge

EUV performance depends on more than source brightness. The machine must maintain source power, vacuum quality, mirror cleanliness, reticle handling, wafer-stage motion, focus, and overlay at the same time. Small contamination or position errors can reduce usable exposure or degrade the printed pattern. This is why an EUV scanner is an integrated source, optics, stage, control, and environmental system rather than simply a shorter-wavelength lamp.

How DUV scanners print larger and less demanding features

Three DUV wavelengths

ASML identifies three principal DUV families:

  • ArF: 193 nm, the shortest-wavelength DUV option and the basis of the highest-resolution DUV patterning.
  • KrF: 248 nm, used for layers whose dimensions and process requirements fit that wavelength.
  • i-line: 365 nm, a mercury-source wavelength used for still larger features and mature process layers.

DUV projection systems use refractive lenses. Unlike EUV, their exposure path can operate in air or a controlled atmosphere because these wavelengths pass through suitable optical materials.

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Why immersion DUV uses water

ArF immersion scanners place a thin water layer between the final projection lens and the wafer. Water raises the effective numerical aperture, allowing the system to resolve finer features than a comparable dry optical path. The liquid must be managed as part of the scan: it has to remain uniform, clean, and correctly positioned while the wafer moves.

Immersion improves optical capability, but it does not turn a DUV tool into an EUV tool. The wavelength remains 193 nm, and the process still relies on refractive lenses and the resist, focus, and overlay limits associated with that system.

Representative resolution by wavelength

ASML’s 2025 annual-report graphic gives representative system resolutions. These figures describe representative capabilities, not a guarantee that every process layer will print at exactly that dimension. Actual results depend on the process, resist, pitch, pattern complexity, focus budget, and required overlay.

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System family Wavelength Optical approach Representative resolution Typical role
EUV 13.5 nm Reflective mirrors in high vacuum 8 nm Smallest and most complex critical layers
ArF DUV 193 nm Refractive projection optics; immersion variants add water 38 nm High-resolution layers that can be patterned with DUV
KrF DUV 248 nm Refractive projection optics 80 nm Less demanding feature sizes
i-line DUV 365 nm Refractive optics using a mercury-source line 220 nm Larger features and mature layers

Why an advanced chip uses EUV and DUV together

An advanced process node does not mean every layer is exposed with EUV. A chip may contain only one or two especially complicated layers that need EUV; the rest can be printed with DUV according to ASML. Contacts, interconnects, memory structures, alignment marks, and other layers have different pitches and tolerances. Using EUV on a layer that DUV can print would add complexity without necessarily improving the device.

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When EUV is selected

  • The layer contains the smallest pitches or most crowded two-dimensional patterns.
  • Printing it with DUV would require additional patterning steps that increase process complexity.
  • The design’s overlay and defect requirements justify EUV’s capability.

When DUV is the better choice

  • The layer’s dimensions fit ArF, KrF, or i-line capability.
  • A mature DUV process offers adequate focus and overlay margin.
  • The fab can obtain the required throughput and cost with an established DUV flow.

This division is an economic and technical decision. EUV reduces the need for some multi-patterning approaches on the tightest layers, while DUV supplies a broad range of capable, productive exposures for the rest of the wafer.

Throughput, overlay, and the economics of a layer

Throughput is usually expressed in wafers per hour, but the number must be tied to a particular scanner, recipe, and operating condition. ASML reported that the NXE:3800E reached its full specification of 220 wafers per hour in 2025. That is a reported specification for that EUV model, not a universal rate for every EUV or DUV machine.

Layer economics include more than scanner speed. A manufacturer weighs exposure time, resist and mask costs, process steps, metrology, defect risk, and the number of patterning cycles needed to reach the target pitch. DUV can be the lower-cost option for a layer even when EUV is technically capable of printing it. Conversely, EUV may be economically preferable for a critical layer if it eliminates several DUV patterning steps.

Overlay is another economic variable because every layer must line up with structures printed earlier. A scanner that exposes quickly but cannot hold the required alignment would not produce usable chips. Focus control, stage stability, reticle handling, and contamination management therefore affect the number of good dies, not just the headline wafer-per-hour figure.

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What happens inside an EUV exposure field

The scanner first establishes a stable vacuum and thermal environment. The source produces EUV radiation, reflective optics collect and shape it, and the reticle presents the layer pattern. Mirrors then reduce and focus that reflected image onto the resist-coated wafer. The wafer stage moves through the scan while sensors and control systems maintain position and focus.

Because the reticle and wafer are not simply placed under a stationary lamp, the machine must coordinate source timing, mirror alignment, reticle motion, wafer motion, and focus in real time. The same exposure concept applies to DUV step-and-scan tools, but EUV’s vacuum and reflective path add additional control points.

High-NA EUV: the next capability increase

High numerical aperture EUV increases the optical acceptance angle so the system can print finer features. ASML and imec’s joint High-NA EUV laboratory uses the TWINSCAN EXE:5000 as an early development platform for logic and memory manufacturers. Their announcement described preparation for high-volume manufacturing in the 2025–2026 timeframe.

Higher NA does not provide a free resolution gain. As NA rises, depth of focus becomes tighter, leaving less tolerance for wafer height variation, resist thickness variation, focus error, and process drift. High-NA programs therefore require stronger focus control, tighter wafer and reticle handling, and process development that can exploit the optical capability without losing yield.

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Common misconceptions and practical limits

“EUV prints the whole chip in one pass.”

It does not. Each reticle represents a layer, and the scanner exposes many fields across a wafer. The wafer then returns for additional lithography and non-lithography steps.

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“A shorter wavelength automatically gives the final feature size.”

Wavelength is fundamental, but resolution also depends on numerical aperture, focus, resist behavior, pattern geometry, and process control. The representative values in the table should not be read as a promise for every layer.

“DUV is obsolete once EUV enters a fab.”

DUV remains necessary for the majority of layers, including layers whose dimensions do not justify EUV. ArF immersion, dry ArF, KrF, and i-line tools occupy different points on the capability and cost curve.

“A consumer UV lamp can reproduce this process.”

It cannot. Semiconductor lithography requires a reticle projection system, wavelength-specific optics, wafer stages, resist and development chemistry, overlay control, metrology, and a tightly managed process line. EUV additionally requires high vacuum and reflective multilayer optics.

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Putting the two technologies into one manufacturing flow

  1. Choose the layer’s patterning method. The process team assigns EUV, ArF immersion, another DUV option, or a combination based on pitch, overlay, process margin, and economics.
  2. Prepare the reticle and recipe. The selected scanner receives the correct reticle, focus settings, illumination conditions, and alignment data for that layer.
  3. Expose the wafer. The scanner steps and scans across all fields while maintaining the required focus and overlay.
  4. Transfer and inspect. Development and etch or related processing turn the resist image into a device layer. Inspection and metrology verify dimensions, defects, and alignment.
  5. Repeat with the next layer. The wafer may move between EUV and several DUV scanner families as the design moves from the smallest critical structures to larger, less demanding features.

The result is a deliberately mixed lithography flow: EUV is reserved for the layers that benefit most from its 13.5 nm wavelength, while DUV supplies the scale, flexibility, and economics needed to complete the rest of the chip.

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