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AI chips are designed from the workload outward. Teams first define the models, data types, memory, interconnect, power and deployment limits. They then choose compute engines and memory architecture, partition functions across one or more dies, verify the implementation with electronic-design-automation (EDA) tools, select a foundry and package, and qualify the finished accelerator inside a server or rack.
The package and the complete system are separate from the compute die. High-bandwidth memory (HBM), interposers, chiplets, host links, cooling and power delivery can determine whether a technically impressive die becomes a usable product.
What AI-chip design actually covers
An AI accelerator is not just a collection of matrix-multiplication units. It is a coordinated design of compute, memory, data movement, software support, packaging and system interfaces. A chip that has high theoretical arithmetic throughput can still perform poorly if its memory cannot feed the engines, if data cannot move between accelerators quickly enough, or if the software stack cannot schedule the workload.
Vendor specifications are useful examples, not universal rules. AMD’s CDNA family shows how matrix cores, HBM, interconnect fabrics and process choices evolve together across generations. TSMC presents its AI and high-performance-computing (HPC) platform as a combination of process technology, advanced packaging, connectivity and an intellectual-property ecosystem rather than as a node number alone.
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How are AI chips designed? The end-to-end process
1. Define the workload and system requirements
Architecture begins with a workload definition. Designers need to know whether the product targets training, inference or both; which model sizes and operators matter; and which numerical formats are required. Lower-precision formats can increase throughput and reduce memory traffic, but only when the model and software can use them without unacceptable accuracy loss.
The requirements document also sets practical limits:
- Memory capacity: how much model, activation and optimizer data must remain close to the accelerator.
- Memory bandwidth: how quickly data must reach compute engines to avoid stalls.
- Host and accelerator links: how the device communicates with CPUs, storage and other accelerators.
- Power and cooling: the electrical and thermal envelope of the board, server and rack.
- Cost and deployment: the package, board, system and manufacturing targets that make the product viable.
- Software: compiler, runtime, libraries and frameworks that must expose the hardware’s capabilities.
There is no universally best architecture. A design optimized for large-batch training may make different choices from one optimized for latency-sensitive inference. The same product family can change its balance of compute, memory and interconnect between generations.
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Architects select the units that perform the target operations and the mechanisms that keep those units busy. AI chips commonly include vector or scalar execution alongside specialized matrix engines, but the exact organization varies by vendor and generation. Matrix hardware is valuable because many neural-network layers can be expressed as large, regular multiplications and accumulations.
Supported data formats are an architectural decision, not merely a software feature. Hardware may provide different paths for formats such as FP32, lower-precision floating point and integer arithmetic. Each path affects area, power, accuracy and compiler scheduling.
On-chip registers, scratchpad memory and cache determine how much data can be reused without going to external memory. Architects model the balance between arithmetic work and data movement: adding more compute units without enough bandwidth can increase peak specifications while leaving real workloads underfed.
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AMD describes its CDNA architecture by discussing matrix cores, HBM and its Infinity Architecture fabric together, while also emphasizing data movement and power efficiency. Those are AMD’s design claims for its products, not a guarantee that every accelerator uses the same engines or fabric.
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3. Design memory and interconnect as part of the architecture
Memory is often the limiting resource in an AI system. Designers choose the amount and type of local memory, cache hierarchy, external memory and links between dies or packages. Capacity determines which models fit; bandwidth determines how quickly weights and activations can be supplied; latency and coherency determine how efficiently different processors cooperate.
HBM places very wide memory interfaces close to the compute silicon. It can provide substantial bandwidth in a compact package, but it also raises package, power-delivery, thermal and manufacturing requirements. HBM therefore belongs in the architecture discussion from the beginning, not as an accessory added after the die is complete.
Interconnect choices cover both on-package die-to-die links and system-level links. They determine how accelerators share data, synchronize work and scale beyond one device. A design with excellent local bandwidth can still be constrained by a slow connection to the host CPU or to neighboring accelerators.
4. Decide whether to use chiplets
Chiplets divide a large function into multiple dies that are assembled in one package. A design might place compute, cache, memory controllers and I/O on separate dies, allowing each function to use a suitable process technology or to be reused across products.
AMD’s CDNA 5 overview describes partitioning compute, memory, cache and I/O functions and integrating compute dies with HBM in an advanced package. This is an AMD implementation description, not an industry-wide blueprint. Other accelerators may use a monolithic die, a different partition or no chiplets at all.
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Chiplets bring trade-offs. Smaller dies can improve reuse and make it possible to combine process technologies, but the package needs reliable die-to-die connections, precise power delivery and a thermal plan. Testing and qualification also become more complex because every die and every interconnection must work together.
5. Select the package and HBM arrangement
Advanced packaging turns separate dies and memory stacks into one electrical and mechanical assembly. TSMC describes its CoWoS technology as a 2.5D packaging approach for HPC and AI. Its CoWoS-R description says a redistribution-layer interposer connects system-on-chip devices and/or HBM; TSMC states that CoWoS-R entered volume production in 2023.
The package affects signal integrity, bandwidth, power delivery, heat removal and board layout. It also limits how many dies and memory stacks can be placed together and how they can be serviced or tested. A package is therefore not the same thing as a compute die: it can contain several active dies, HBM stacks, an interposer and passive elements.
Vendor examples: specifications with their generation attached
The following figures are vendor-published specifications for named products or generations. They are not independent benchmark results and should not be generalized to all AI chips.
| AMD generation or family | Process information listed by AMD | HBM capacity | Maximum bandwidth |
|---|---|---|---|
| CDNA | 7nm FinFET | Not stated in the cited overview | Not stated in the cited overview |
| CDNA 4 / MI350 Series | Combination including 3nm and 6nm FinFET | Up to 288 GB HBM3E | Up to 8 TB/s |
| CDNA 5 / MI400 Series | Forward-looking specification on AMD’s overview | 432 GB HBM4 | Up to 23.3 TB/s |
AMD’s CDNA 5 figures are forward-looking specifications on the page reviewed and may change before products ship. A smaller process-node number also does not, by itself, prove that one accelerator is faster or more efficient than another.
6. Describe the design in RTL and verify it
Once the architecture is defined, hardware teams describe digital logic in register-transfer level (RTL) languages. EDA tools then transform and analyze that description through design implementation and sign-off. In broad terms, the work includes synthesis, physical planning, placement and routing, timing and power analysis, verification, and preparation of manufacturing data.
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Verification operates at several levels. Simulation and formal methods check that logic behaves as intended; hardware emulation or prototyping can exercise larger software workloads; and physical sign-off checks whether timing, power, signal integrity and manufacturing rules are satisfied. Bugs found after masks are made are extremely expensive, so teams iterate between architecture, RTL, physical implementation and verification.
NVIDIA describes GPU-accelerated EDA as a way to compress the path from RTL to sign-off. That is a vendor description of its workflow and should not be read as an independently measured, industry-wide improvement.
7. Choose a foundry process
The foundry process determines transistor options, wiring layers, design rules, available memory and logic libraries, manufacturing capacity and supported packaging flows. Process selection happens alongside architecture because it changes what can fit on a die, how much power it consumes and which interfaces are practical.
TSMC’s HPC platform explicitly combines process technology with advanced packaging, connectivity and IP, and notes heterogeneous integration alongside leading-edge processes. This is why a process label is incomplete as a product description. Node names from different foundries are not a neutral, one-to-one performance scale, and the cited material does not provide a controlled cross-foundry comparison.
8. Move from verified implementation to manufacturing
After sign-off, the design is converted into the data used to create masks and manufacture wafers, then the resulting dies are electrically tested. Good dies are assembled with HBM and other package elements, tested again and integrated onto boards or modules.
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Why system integration changes the chip design
An accelerator is qualified as part of a platform, not in isolation. Engineers must validate host connectivity, memory coherency where supported, scale-up links among accelerators, board power, voltage regulation, cooling, firmware, drivers and workload behavior. Rack density and serviceability can force changes to package limits and operating points.
NVIDIA’s Grace Hopper article, published November 10, 2022, illustrates this system-level approach. NVIDIA reported a 900 GB/s NVLink-C2C connection, up to 72 Arm Neoverse V2 CPU cores and up to 96 GB of HBM3 on the Hopper GPU for that platform. These are dated, platform-specific figures, not current market-leading specifications or universal values for AI accelerators.
In a corporate announcement about custom XPU deployment, NVIDIA and MediaTek describe the need to integrate multi-die designs, HBM, I/O, packaging, networking, qualification and rack-scale technologies. The announcement quotes GUC chair and chief strategy officer Lie-Szu Juang: “NVLink Fusion allows the hyperscalers or the custom ASIC designers to integrate their own custom CPU or XPU and bridges the NVIDIA technology with a third-party process to create a unified rack-scale architecture.” The statement is a corporate perspective, not an independent assessment.
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How chiplets and HBM help—and what they complicate
Benefits
- Function-specific processes: compute, I/O, cache and memory interfaces can be implemented on dies suited to their needs.
- Design reuse: a chiplet can potentially be reused across products or combined in different configurations.
- Shorter data paths: HBM and on-package links place high-bandwidth resources near compute.
- Scaling options: multiple dies can provide more aggregate compute or memory than a practical single die.
Costs and risks
- Package complexity: interposers, redistribution layers and fine-pitch connections increase assembly demands.
- Thermal concentration: several active dies and HBM stacks share a constrained cooling path.
- Power delivery: the package and board must deliver current with acceptable voltage noise.
- Verification: die-to-die protocols and interactions add cases to simulate and validate.
- Yield and test: every die, connection and assembled package must meet specifications.
- Software exposure: compilers and runtimes must schedule work across the partitioned resources.
What a complete design decision should compare
Teams should compare candidate architectures on the workload and data type they actually target, not on one peak-throughput figure. Useful questions include:
- How much model and intermediate data fits in local and HBM memory?
- What sustained bandwidth is available under the intended power and thermal limits?
- How much performance is lost to communication, synchronization and host transfers?
- Does a monolithic die or a chiplet package provide the better cost, yield and schedule?
- Can the chosen foundry process and package supply the required IP and interfaces?
- Are compiler, library and framework support mature for the selected formats and engines?
- Can the board, server and rack remove heat and deliver power at the planned density?
These questions explain why two accelerators with similar peak arithmetic numbers can behave very differently in a production system. The meaningful comparison is the complete path from model operation to delivered result per watt, per dollar and per unit of rack capacity; the supplied vendor sources do not provide a controlled cross-vendor benchmark for that comparison.
The practical takeaway
AI-chip design is a chain of linked decisions. Workload requirements shape compute and data formats; memory and interconnect shape the architecture; chiplets and HBM shape the package; EDA tools turn the architecture into a verified physical implementation; the foundry and packaging flow determine what can be manufactured; and system qualification determines whether the accelerator works in a powered, cooled, networked server or rack.
Reading any single specification in isolation—especially a process node, matrix-throughput number or memory-bandwidth claim—misses most of the engineering. The finished product is the die, package, board, software and system working together.
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