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AI chipmakers choose a foundry by matching the logic dies, package architecture, HBM configuration, design ecosystem, qualified production capacity, and delivery schedule—not by selecting a process node in isolation. The right partner is the one that can qualify the complete design and supply plan for a particular accelerator; vendor technology descriptions alone do not establish a universal winner.
Why packaging and HBM change the foundry decision
An AI accelerator is not just a logic die. Its package may bring together multiple compute dies and high-bandwidth memory (HBM) stacks, with the package’s interconnect linking those components. That makes packaging a design choice as well as a manufacturing and sourcing choice: the chipmaker must plan the logic, memory, package, and production route as a connected system.
The package architecture shapes how those components are placed and connected. It can affect which designs are feasible, how the chip is partitioned across dies, and what package and memory interfaces the design team must support. Those consequences make it risky to finish the logic design first and treat packaging as a late-stage assembly decision.
For example, TSMC describes CoWoS as a 2.5D packaging technology for high-performance computing (HPC) and AI. Its annual-report chapter says CoWoS integrates multiple SoC chips and HBM stacks for HPC products. That is a description of TSMC’s offering, not independent evidence that it will outperform another supplier for a given design. TSMC’s CoWoS technology page and its 2025 annual-report chapter explain the company’s published approach.
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Start with the package architecture
Before comparing foundries, the chipmaker needs a package concept: which logic dies and HBM stacks belong in the package, how they connect, and whether the design relies on side-by-side integration, bridges, or vertical stacking. The terminology and capabilities differ among suppliers, and the public descriptions below do not provide a neutral, like-for-like benchmark.
| Supplier and approach | What the public source describes | What it does not establish |
|---|---|---|
| TSMC: CoWoS and SoIC/3DFabric | CoWoS is described as 2.5D packaging for HPC and AI. CoWoS-R uses an RDL interposer to connect SoC and/or HBM; TSMC says this service has been in volume production since 2023. TSMC’s 2025 annual report says 3nm SoIC stacking entered volume production in 2025. CoWoS page; 2025 annual report. | Customer-specific package qualification, allocation, yield, cost, or comparative performance. |
| Intel: EMIB, EMIB-T, and Foveros | Intel describes silicon bridges through EMIB, stacking through Foveros, and EMIB-T. Intel says EMIB-T adds channels through the bridge for power delivery and routing needs associated with newer HBM technologies. Intel’s advanced-packaging article. | Independent comparative measurements or customer-specific availability and qualification. |
| Samsung: Chip-on-Wafer and heterogeneous integration | Samsung describes Chip-on-Wafer (CoW) technology for 2.5D packages with higher HBM module counts, and says it is developing fine-pitch bumpless hybrid copper bonding for HPC. Samsung’s heterogeneous-integration page. | Independent package comparisons, completed qualification for a particular design, or broadly orderable capacity. |
These descriptions are useful for identifying architectures worth evaluating, not for declaring one superior. A chipmaker should ask each candidate to map the proposed package to the exact die and memory arrangement, interface requirements, design rules, and qualification plan. If a roadmap capability is essential, ask whether it is available for the project’s intended production window rather than treating a development announcement as a deliverable.
Match HBM requirements to the package and supply plan
HBM selection is tied to the package design. The chipmaker needs to settle the number and arrangement of stacks, the required memory interface, and how those stacks connect to the logic. A package that supports HBM in general is not automatically qualified for every stack configuration or accelerator design.
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Foundry materials establish that HBM is integrated into some of the package offerings described above, but they do not disclose customer-specific HBM allocations or supplier commitments. Consequently, public technology pages cannot answer whether enough qualified memory will be available for a particular product’s ramp.
- Specify the required HBM configuration and interface before seeking a package commitment.
- Ask which memory suppliers and stack versions are included in the proposed qualification, and who is responsible for securing supply.
- Confirm whether memory sourcing, package assembly, and logic-wafer production are coordinated under one operating plan or require separate contracts and forecasts.
- Request design-specific confirmation of qualification status and planned quantities; do not infer allocation from a technology announcement.
That last distinction matters in multi-party supply chains. A foundry’s package capability does not, by itself, prove that a chipmaker has secured HBM, that a specific package has passed qualification, or that the complete system can ship on the desired schedule.
Check logic-process fit and design enablement
The logic process must meet the design’s requirements, but a node name alone does not settle the choice. Die partitioning, design rules, package constraints, and supporting tools and IP all affect whether the design can be implemented and qualified. The chipmaker should evaluate the actual design flow that will be used across the logic dies and package, including how early package decisions feed back into logic design.
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Consider the operating model as well as the process. TSMC presents its HPC platform as combining wafer technology, its Open Innovation Platform design ecosystem, and 3DFabric packaging. That illustrates an integrated platform approach in TSMC’s own description; it is not a neutral assessment of how well another supplier’s ecosystem supports a particular project. TSMC’s HPC platform page describes that combination.
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During evaluation, ask the design and packaging teams to identify which rules, tools, IP, and partner support are needed for the chosen architecture. Establish who owns interface decisions and design changes when logic, HBM, and package teams are working across organizational boundaries. A technically suitable process can still be a poor project fit if the required design enablement or coordination is not in place.
Separate production evidence from roadmap timing
Packaging announcements can refer to very different stages: development, certification, reported volume production, or a future production target. These are not interchangeable. The schedule should be based on evidence appropriate to the exact technology and package the chipmaker intends to use.
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- Reported production milestone: TSMC says its CoWoS-R service has been in volume production since 2023, and its 2025 annual-report chapter says 3nm SoIC stacking entered volume production in 2025. Those are published company claims about specific offerings; they do not demonstrate qualification or capacity for an individual customer’s package.
- Certified capability with a stated future ramp: TSMC’s HPC page says a CoWoS solution for interposers 5.5 times mask/reticle size was certified in 2025 and would initiate volume production in 2026. The page states a plan; that statement alone does not confirm that the planned ramp was completed. TSMC’s HPC platform page.
- Development work: Samsung says it is developing fine-pitch bumpless hybrid copper bonding for HPC. Development work should be treated as a capability under development, not as evidence that the process is already qualified for the chipmaker’s design.
For each milestone relevant to the project, obtain the current status, the definition of readiness being used, and the remaining qualification steps. The dates above describe vendor-reported milestones or plans, not a guarantee that a new customer can enter production on those dates.
Treat partnerships as signals, not supply guarantees
Partnership announcements can indicate how suppliers are positioning for next-generation AI products, but a collaboration is not proof that a package is generally available, qualified for every customer, or backed by a specific allocation. Samsung’s July 25, 2026 announcement says it and Broadcom plan to pursue HBM supply and advanced-packaging collaboration, including 2.3D and 2.5D integration for next-generation AI accelerators. It is a named partnership signal, not a universal purchasing or qualification commitment. Samsung’s announcement.
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For a chipmaker, the practical question is whether a particular collaboration covers the required configuration and commercial plan. Ask which organizations are responsible for the logic, package, and memory, what is already qualified, and which decisions or supplies remain contingent. Record those answers against the project schedule instead of treating a broad announcement as a completed operational arrangement.
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Use a design-specific procurement scorecard
Several decisive procurement values are not available as neutral, directly comparable figures in the public sources cited here: qualified capacity, customer-specific HBM availability, cost, yield, lead time, and delivered system-level performance. They require design-specific evidence and quotations. A useful scorecard therefore distinguishes published capability from commitments the supplier must substantiate for the project.
| Decision area | Evidence or answer to request | Why it matters |
|---|---|---|
| Package architecture | Proposed interposer, bridge, or stacking approach; which logic dies and HBM stacks are included; required interfaces. | Confirms that the offered package maps to the planned design rather than just sharing a broad technology label. |
| Design enablement | Applicable process and package design rules, supporting tools and IP, and named responsibility for cross-team integration. | Surfaces design-flow gaps and coordination dependencies before they threaten schedule. |
| HBM readiness | Stack configuration, supplier commitments, qualification status, and planned quantities for the project. | Separates package capability from actual memory supply and design qualification. |
| Production maturity | Status for the exact package option, evidence of completed qualification, remaining milestones, and the intended ramp window. | Prevents development or roadmap language from being mistaken for a production-ready route. |
| Commercial and delivery terms | Design-specific quotation, capacity commitment, expected lead time, yield assumptions, and any conditions on the schedule. | These values are not established comparably by vendor technology pages and must be assessed for the actual project. |
| Performance evidence | Measurements for the complete design under stated test conditions, where available and relevant. | Vendor feature descriptions do not constitute a neutral, system-level comparison. |
Do not compress the scorecard into a single foundry ranking until the team has agreed how to weight schedule risk, design fit, supply assurance, and performance evidence. A supplier may be attractive on architecture yet fail the project’s timing or memory-supply requirements; another may fit the schedule but require a different die partition or operating model. The correct choice is conditional on the design and the evidence obtained for it.
A practical selection sequence
- Freeze the problem definition: document the intended logic dies, HBM configuration, package concept, product schedule, and required production scale.
- Shortlist architectures: compare the relevant interposer, bridge, and stacking approaches against that design. Exclude options that cannot support a required connection or package arrangement.
- Review design readiness: ask each candidate how its logic process, package rules, tools, IP, and integration support apply to the proposed implementation.
- Verify HBM and qualification: obtain configuration-specific confirmation of memory supply responsibilities, package qualification, and remaining validation steps.
- Validate the ramp: distinguish completed production milestones from certification, development, and future targets; request a project-specific schedule and capacity commitment.
- Compare commercial evidence: evaluate quotations, lead times, yield assumptions, and capacity on a consistent design basis rather than filling gaps with industry-wide guesses.
- Make the decision conditional: document the evidence, unresolved dependencies, owners, and milestones that must be met before committing to production.
This sequence keeps early architecture decisions connected to downstream procurement. It also gives the chipmaker clear decision gates: if memory supply, package qualification, design enablement, or the production ramp cannot be substantiated, the team can revisit the architecture before the product schedule depends on it.
What public information can—and cannot—tell you
Official technology pages and company announcements are appropriate sources for what a supplier says it offers and for the milestones it reports. They are not a substitute for a neutral comparison of yield, pricing, qualified capacity, customer allocations, lead times, or end-to-end performance. In particular, this set of published descriptions does not support a categorical claim that one foundry is best for all AI accelerators.
Use public material to form a shortlist and frame diligence questions. Make the final choice from design-specific qualification evidence, supply commitments, schedule assumptions, and commercial terms. If the project depends on a capability described as forthcoming or in development, make confirmation of its actual readiness a formal decision gate.
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