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AI chips are produced through a chain of specialized roles, not by one company performing every step. A chip designer defines the architecture and specifications; a foundry fabricates the design on silicon wafers; memory suppliers provide high-bandwidth memory (HBM); packaging specialists connect compute dies and memory; and system makers install the packaged accelerators with CPUs, networking and cooling in data-center racks.
This division explains why an accelerator can be technically ready yet constrained by HBM, advanced packaging capacity or rack integration. It also explains why announcements about new fabs and packaging lines must be separated from factories already producing chips.
The AI chip supply chain at a glance
An AI accelerator becomes useful only after several handoffs. The logical sequence is:
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- Architecture and design: a chip company specifies the compute engines, memory interfaces, interconnects, power targets and software features.
- Wafer fabrication: a semiconductor foundry patterns that design onto silicon wafers using a chosen process technology.
- Memory production: HBM stacks provide very high bandwidth near the compute dies.
- Advanced packaging: the processor dies, HBM stacks and sometimes additional chiplets are assembled into one package with extremely dense connections.
- System integration: a server or rack maker combines accelerators with CPUs, switches, networking, power delivery and cooling.
- Data-center deployment: completed racks are connected into clusters, supplied with software and operated as an integrated computing platform.
Each stage has its own equipment, yield limits, qualification work and delivery schedule. A shortage at any one stage can delay the final system even when other stages have spare capacity.
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1. Design and foundry roles are different
What the designer does
The design company decides what the accelerator is intended to do. Engineers define the processing units, on-chip memory, external memory interfaces, security features, power envelope and links used to communicate with other chips. They turn those requirements into a physical layout and manufacturing rules that a foundry can use.
Designers may be fabless, meaning they contract manufacturing rather than owning the wafer factories that produce their chips. Their work still includes verification, software support, package definition and qualification with memory and system partners. A design is not a finished product until it has been manufactured, packaged and tested.
What a pure-play foundry does
TSMC describes itself as a pure-play foundry: it manufactures products designed by customers and says it does not design, manufacture or market semiconductor products under its own name. That model helped enable the fabless industry, but it should not be treated as a rule for every semiconductor business; some companies combine design and manufacturing.
Fabrication starts with a processed wafer. Repeated deposition, lithography, etching, implantation and cleaning steps create transistors and multiple layers of metal interconnect. The foundry monitors defect density and electrical performance, then tests dies on the wafer before they are separated for packaging. The process node name is only one part of the specification; the design, package, memory configuration and power delivery also affect the final accelerator.
Where fabrication is operating versus planned
TSMC’s 2024 annual report states that its first Arizona fab entered high-volume production with the N4 process in the fourth quarter of 2024. The same report describes manufacturing in Taiwan and subsidiaries in Japan, China and the United States, alongside plans for additional facilities. An operating fab and a proposed or constructed facility are not interchangeable: a location can be announced, under construction, qualifying equipment or in production at different times.
Capacity planning is therefore a continuing business decision rather than a one-time announcement. TSMC chairman and CEO C.C. Wei wrote in the company’s 2024 annual report: “We employ a disciplined and thorough capacity planning system to evaluate and judge the structural increase in the long-term market demand profile, to determine the appropriate capacity to build.” This is a statement of the company’s planning approach, not an independent forecast of demand.
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2. Wafer fabrication is only the midpoint
A wafer contains many individual dies. After electrical tests, good dies are cut apart and prepared for assembly. For conventional processors, a package may provide pins or contacts and basic protection. AI accelerators require much more: wide memory interfaces, short high-speed connections, substantial power delivery and a way to remove heat from a densely active package.
Packaging determines how close compute and memory can be placed, how many signals can cross between them and how much power the assembly can handle. It also affects test procedures, substrate supply, reliability qualification and the ability to replace or combine dies. Consequently, a chip can be available at the wafer stage while packaged units remain constrained.
Advanced packaging technologies
TSMC identifies several technologies, including CoWoS, InFO and SoIC. CoWoS is a 2.5D platform in which dies sit side by side on an interposer or similar high-density substrate, allowing very wide connections without placing every function on one monolithic die. InFO is a fan-out approach used for compact, high-density packages. SoIC is a three-dimensional chip-stacking technology that bonds dies vertically.
TSMC’s 2024 report says CoWoS-L entered volume production in 2024 for high-performance-computing products. That fact applies to the named platform and period; it does not mean every AI accelerator uses CoWoS-L or that all advanced-packaging capacity is interchangeable. Different products use different package designs, substrates and qualification paths.
3. What HBM is and why AI GPUs need it
HBM in practical terms
High-bandwidth memory is a stack of memory dies connected vertically and linked to a processor through a very wide interface. The stack sits close to the compute die in the package, reducing the distance data must travel. Instead of relying only on a small amount of on-chip memory, an accelerator can stream model weights, activations and intermediate results from several HBM stacks.
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AI training and inference repeatedly move large data sets. Arithmetic units can remain underused if they wait for memory, so bandwidth is a key design constraint alongside compute throughput. HBM does not make an accelerator faster in every workload, but it supplies the data rate needed by bandwidth-intensive neural-network operations.
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Why HBM is a supply-chain bottleneck
HBM requires specialized memory dies, vertical stacking, through-silicon connections, testing and a package that can route many signals between memory and compute. Those steps add dependencies beyond ordinary wafer fabrication. NIST’s profile of the SK hynix project identifies HBM as one of the core AI supply-chain constraints and a crucial GPU component for training AI systems.
NIST reports that SK hynix attributes up to 1.18 terabytes of data per second to its latest HBM in the context of a planned next-generation facility. This is a vendor figure reported by NIST, not a market-wide HBM statistic or an independent benchmark.
Announced capacity is not delivered capacity
The NIST profile says the planned SK hynix advanced-packaging line in West Lafayette is expected to begin mass production in the second half of 2028. That is a future schedule. It should not be counted as HBM or packaging output available today, and project timing can change as construction, equipment installation and qualification proceed.
4. How advanced packaging joins compute and memory
From separate dies to one accelerator package
Packaging engineers first select a physical arrangement: compute dies beside HBM stacks, stacked logic and memory, or a combination of chiplets. An interposer, bridge or other high-density connection layer carries thousands of signals. The assembly is then attached to a package substrate that connects to the server board.
The package must meet electrical, mechanical and thermal requirements simultaneously. Shorter connections improve signal integrity and energy efficiency, while the large active area increases heat flux. The package also has to survive thermal cycling and manufacturing variation. Testing can occur at wafer, die, package and system levels, with failures at any level reducing usable output.
Why packaging capacity can limit shipments
Adding wafer-fab capacity does not automatically add the ability to assemble large AI packages. Advanced packaging uses dedicated tools, substrates, interposers and skilled process capacity. A product may therefore face a packaging queue even when its compute dies and HBM stacks have been manufactured. This is why supply-chain analysis must track fabrication and packaging as separate stages.
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5. From a packaged accelerator to a data-center rack
A packaged accelerator is a component, not a complete computing service. System makers place accelerator modules on server boards, connect them to host CPUs, add network interfaces and switches, and design power and cooling for sustained operation. Firmware, drivers and cluster software then make the hardware usable for training or inference.
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Example: NVIDIA GB200 NVL72
NVIDIA’s GB200 NVL72 documentation describes a rack-scale system combining 36 Grace CPUs and 72 Blackwell GPUs. The rack uses NVLink for GPU-to-GPU communication, data-center networking and liquid cooling. NVIDIA lists 130 terabytes per second of communication for the NVLink Switch System in that rack.
These figures describe the specified GB200 NVL72 configuration, not every AI server. The rack’s performance depends on its complete interconnect, software and workload. NVIDIA also publishes benchmark comparisons and marks projected performance as subject to change; any such result must be read with the company’s stated test conditions rather than generalized to all deployments.
Why networking and cooling matter
Large models are distributed across many GPUs. The rack therefore needs predictable low-latency links for exchanging tensors and synchronizing work. External networking connects racks into a larger cluster and moves data to storage and other services. Power systems must deliver high current while protecting components from faults.
Air cooling may be insufficient for the heat density of a tightly integrated rack. Liquid cooling uses cold plates, manifolds and heat exchangers to remove heat more effectively, but it adds facility plumbing, leak controls and maintenance requirements. The cooling choice is a system-level decision made with the rack’s power and layout, not a property of the GPU die alone.
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Governments are funding projects across multiple links rather than treating leading-edge logic as the only requirement. The U.S. Government Accountability Office reported on December 11, 2025, that the Department of Commerce had awarded $30.9 billion in direct funding across 40 projects by July 2025. The projects span stages from materials production to packaging.
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GAO also reported Commerce’s estimate that the projects could raise the U.S. share of global leading-edge logic manufacturing from 0 percent in 2022 to an estimated 20 percent by 2030. That is a target estimate, not an achieved result. GAO said companies expected project completion dates to run through 2033, so awards and construction schedules should not be interpreted as immediate production.
How to read a capacity announcement
- Award: public funding has been committed under stated conditions; physical output may be years away.
- Construction: buildings or infrastructure are being developed, but tools may not yet be installed.
- Qualification: equipment is producing test wafers or packages while processes are being validated.
- Volume production: the facility is making qualified products at commercial scale, subject to yield and customer demand.
Comparing supply-chain examples without mixing stages
| Comparison axis | What to ask | Evidence in the named examples |
|---|---|---|
| Design versus foundry | Who specifies the chip, and who fabricates it? | TSMC describes a pure-play foundry manufacturing customer designs; the customer remains the design owner. |
| Fabrication process and location | Which process is operating, and where? | TSMC reports N4 high-volume production in Arizona in Q4 2024, with manufacturing and subsidiaries in several countries. |
| Packaging method and capacity | Which package is used, and is capacity operating or planned? | TSMC lists CoWoS, InFO and SoIC; CoWoS-L entered volume production for HPC products in 2024. |
| HBM availability | Is the memory produced now or part of a future project? | NIST identifies HBM as a constraint and gives a West Lafayette mass-production expectation for the second half of 2028. |
| Rack interconnect, networking and cooling | How are accelerators linked and cooled at system scale? | NVIDIA’s GB200 NVL72 documentation specifies 36 Grace CPUs, 72 Blackwell GPUs, NVLink, networking and liquid cooling. |
| Status of the capacity claim | Is it production, an award, an estimate or a plan? | GAO’s $30.9 billion figure covers awards through July 2025; completion dates extend through 2033. |
These axes help prevent a common error: comparing a working fab with a proposed packaging line, or comparing a memory bandwidth claim with a complete rack’s communication capacity. The available evidence does not establish a comprehensive market-share ranking for every supplier or stage.
Common supply-chain failure points
- Design tape-out delays: verification or software changes can postpone the first wafers.
- Wafer yield problems: defects reduce the number of usable dies and may require process adjustments.
- HBM allocation: memory-stack capacity and qualification can limit finished accelerator volume.
- Packaging bottlenecks: interposers, substrates, bonding tools or test capacity can constrain output after fabrication.
- Thermal and power redesign: a rack may need new cooling or power hardware even when the accelerator package is ready.
- System qualification: firmware, drivers and network behavior must be validated across the complete rack.
These are dependencies, not proof that a particular supplier is failing. The named sources provide examples and project facts, not a complete map of equipment, materials, assembly, server-integration or cloud-provider market shares.
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AI chip manufacturing is best understood as coordinated specialization. Design companies create the architecture; foundries turn designs into wafers; memory suppliers produce HBM; advanced-packaging operations combine the parts; and system makers build cooled, networked racks. The practical availability of an AI accelerator is determined by the slowest qualified stage, not by wafer output alone.
When evaluating a supply claim, check four things: the stage being discussed, the location and process, whether the statement describes operating production or a future plan, and the date and attribution of any performance number. That discipline keeps announcements, estimates and delivered systems from being treated as the same thing.
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