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NVIDIA and ChipAgents have introduced Build-A-Chip-Bench, an evaluation designed to test whether AI agents can take a digital integrated-circuit project from a written specification through architecture, implementation and verified GDS. It is intended as a measure of progress toward autonomous semiconductor engineering, rather than another test of whether a model can generate RTL code.
The first announced results expose a large gap between functional correctness and physically viable silicon: agents passed functional verification on about 40% of tasks on average, but only approximately 10% met the required performance, power and area targets.
What Build-A-Chip-Bench evaluates
ChipAgents announced the benchmark on October 14, 2026, in collaboration with NVIDIA. A benchmark task starts with a chip specification and is expected to continue through the engineering steps needed to produce a physically checked digital design.
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- Architecture and microarchitecture
- Register-transfer-level (RTL) implementation
- Functional verification
- Logic synthesis
- Floor planning
- Standard-cell placement
- Clock-tree synthesis
- Routing
- Timing and power signoff
- Physical verification and generation of a verified GDS database
That sequence matters because each stage constrains the next. A design can simulate correctly and still fail timing closure, exceed its power budget, occupy too much silicon, violate routing rules or fail physical verification. Build-A-Chip-Bench requires those conditions to be satisfied together, not checked as isolated software outputs.
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Why this is harder than an RTL benchmark
Many earlier hardware-AI evaluations concentrate on generating RTL or proving that RTL behaves correctly in simulation. Those are useful capabilities, but they stop before the physical effects that determine whether a design can be manufactured within its limits.
Build-A-Chip-Bench adds a closed loop between high-level decisions and physical feedback. An agent must preserve validated behavior while revising a design, operate specialized electronic-design-automation tools, and reason about trade-offs that only become visible after synthesis, placement and routing. Improving frequency may increase area or power; reducing area can make timing closure harder; a locally valid change can create a later routing or verification failure.
NVIDIA vice president and general manager Tim Costa described chip design as “a defining test of AI’s ability to make decisions that hold up under the demands of the physical world.” ChipAgents founder and CEO William Wang said the company sees a need for “chip superintelligence” as designs become more complex and time-to-market pressure rises.
What the initial scores mean
| Measure | Initial reported result | What it indicates |
|---|---|---|
| Functional verification | About 40% of tasks passed on average | Agents could produce behaviorally valid designs for a substantial minority of tasks. |
| Physical PPA targets | Approximately 10% of tasks met the required performance, power and area targets | Far fewer designs remained viable after physical implementation and constraint checking. |
| Best agent in the reported evaluation summary | Anthropic’s Fable 5.1: 16.6% | A score reported by Bloomberg Law in a contemporaneous summary of The Information; the summary does not establish that it is directly comparable to every aggregate figure in the release. |
The percentages are initial, company-announced results, not an independent industry benchmark or a claim that 10% of designs are ready to manufacture. They show that functional RTL success is materially easier than completing the full implementation flow under simultaneous performance, power and area constraints.
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Which AI system performed best?
Bloomberg Law’s contemporaneous account of reporting by The Information identified Anthropic’s Fable 5.1 as the best-performing agent in the evaluation summary, with a 16.6% score. The available account does not provide a complete public task corpus, test harness, ranking table or independent audit, so the figure should be read as a reported result from this initial evaluation rather than a definitive league table.
ChipAgents also describes Renoir as a domain-specialized model and agent system for chip design and verification. According to the company’s July 26, 2026 collaboration post, Renoir uses NVIDIA Megatron Core for scalable training, NeMo Megatron Bridge for checkpoint conversion and training workflows, and NVIDIA Model Optimizer for quantization and inference efficiency.
ChipAgents says Renoir approaches Claude Fable 5 performance on an internal chip-design benchmark at as little as 22% of the cost. That is a company-reported internal comparison; it is not a Build-A-Chip-Bench score and has not been presented as an independent cost study.
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Does this mean AI can design a chip all the way to tapeout?
Not yet. The benchmark is designed to run through physical implementation and verified GDS, which is a major step beyond RTL generation. A verified GDS database is the layout deliverable used before manufacturing, but passing this evaluation is not the same as an autonomous production tapeout.
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The announced results cover only the initial evaluation. The available information does not identify the full task set, disclose independent replication or audit procedures, or name customers using the agents to tape out commercial silicon. The results therefore demonstrate a challenging capability target and a measurable gap, not proof that an AI system can independently own a complete manufacturing program.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to interpret the benchmark as it develops
Future comparisons will be most useful when they report more than a single pass rate. The important questions are:
- What percentage of tasks pass functional verification?
- How often do designs meet timing, power and area targets simultaneously?
- Can the agent complete synthesis, placement, routing and physical verification without manual intervention?
- Does it maintain correctness while iterating across abstraction levels?
- Are the tasks, tool versions, constraints and random seeds public enough for reproduction?
- What is the cost per successfully completed design, rather than the cost per model run?
Those criteria distinguish a model that writes plausible hardware from an engineering system that can plan, use tools, learn from physical feedback and deliver a constraint-compliant implementation.
Why the NVIDIA–ChipAgents collaboration matters
ChipAgents’ Kexun Zhang says semiconductor design requires “a different class of AI system.” Build-A-Chip-Bench puts that claim under an end-to-end test: the agent must coordinate specialized tools and preserve intent from specification through layout, where mistakes become expensive to detect and correct.
For the industry, the 40%-versus-10% split is the clearest signal so far. AI systems are already capable of producing functionally acceptable results on some chip tasks, but physical design remains the bottleneck. Progress will depend on better long-horizon planning, reliable tool use, stronger optimization under competing constraints and evaluations that outside teams can reproduce.
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