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High-NA EUV keeps the same 13.5 nm light used by conventional EUV, but increases the projection system’s numerical aperture from 0.33 to 0.55. That change lets a scanner resolve finer patterns and may allow some chip layers to be printed with fewer exposures. It also tightens focus and process-control demands, and requires a substantially redesigned tool. As of September 2026, High-NA EUV is in selective production use as well as research and qualification; it has not replaced conventional EUV across chip manufacturing.
What EUV and High-NA EUV mean
EUV lithography uses extreme ultraviolet light with a wavelength of 13.5 nm to project a pattern onto a photosensitive material on a silicon wafer. “High-NA” does not mean a different wavelength or a new process-node name. It describes a newer optical system with a higher numerical aperture (NA): ASML’s conventional NXE systems use 0.33 NA, while its EXE High-NA systems use 0.55 NA.
Numerical aperture describes how much light an optical system can collect and focus. Raising it gives the projection system more ability to resolve small details in the mask pattern on the wafer. ASML identifies an 8 nm critical dimension for EXE in its High-NA explainer. That figure describes a capability of the scanner, not the size of every feature on a chip, a transistor’s complete dimensions, or the meaning of a “2 nm” process label.
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That distinction also helps answer a common question: High-NA is not a separate kind of EUV light. The wavelength remains 13.5 nm; the change is in how the projection optics gather and focus that light. In practical terms, a manufacturer comparing 0.33 NA with 0.55 NA is comparing scanner generations and their imaging capabilities, not two different wavelengths or two direct measurements of chip dimensions.
What changes between conventional EUV and High-NA EUV
| Manufacturing factor | Conventional EUV | High-NA EUV | What the difference means |
|---|---|---|---|
| EUV wavelength | 13.5 nm (ASML lithography principles and High-NA explainer) | 13.5 nm (ASML High-NA explainer) | The light wavelength stays the same; the projection optics change. |
| Numerical aperture | 0.33 on ASML NXE systems (ASML High-NA explainer) | 0.55 on ASML EXE systems (ASML High-NA explainer) | Higher NA supports finer image resolution. |
| Quoted critical dimension | Not stated in the cited sources as a general NXE value. | 8 nm, as described by ASML for EXE. | A scanner capability is not a universal chip-feature size or process-node definition. |
| Depth of focus | Greater than the High-NA system’s, according to imec’s discussion of the High-NA trade-off; a numerical value is not stated. | Reduced relative to 0.33 NA, according to imec; a numerical value is not stated. | Higher resolution comes with a narrower focus window that makes process control more demanding. |
| Optical design | Prior-generation EUV optical design. | New optical design, including anamorphic optics; imec describes its mirrors as twice as large and ten times heavier than those in the prior generation. | High-NA requires a platform-level equipment redesign, not a simple adjustment to an existing scanner. |
| Patterning exposures | Some patterns may need multiple patterning steps. | Some patterns may be printable in one exposure where 0.33 NA would need multiple steps (ASML). | Potential reductions in exposures apply to selected patterns and layers, not automatically to an entire chip. |
| Production economics | No universal cost-per-layer comparison is stated. | No universal cost-per-layer comparison is stated. | Exposure count alone cannot establish which approach costs less after masks, throughput, yield and integration are considered. |
Why higher NA can reduce patterning steps
A chip is built from many patterned layers. If a desired pattern is too fine for one exposure on a particular layer, manufacturers may use multiple patterning steps to form it. Those extra steps can add process operations and coordination across the layer. Because 0.55 NA can resolve finer images than 0.33 NA, High-NA may print some patterns in a single exposure that would otherwise require double or triple patterning.
That is a possible layer-level simplification, not a blanket promise that High-NA will halve or otherwise reduce the number of steps for every chip. The outcome depends on the pattern and layer design: some may benefit from fewer exposures, while others may not. ASML’s 2024 materials describe reduced double or triple patterning as a potential benefit. Whether it improves manufacturing economics also depends on the exposure count, tool throughput, masks, yield and integration with the rest of the process.
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Imec reported a research demonstration of 16 nm-pitch line-and-space patterns in single-print images in 2024, using an ASML TWINSCAN EXE:5000 in its joint High-NA lab. Pitch is the repeated spacing of a pattern, not a standalone measure of production yield or finished-chip performance. The demonstration is evidence of a research capability under those conditions; it is not a commercial product statistic or proof that all production layers can use a single exposure.
The useful manufacturing question is therefore not “Can High-NA print smaller?” in isolation. It is whether a particular layer’s layout can take advantage of the finer imaging to avoid patterning steps, while still meeting alignment, focus and process requirements. A research image of a single-print pattern establishes that a pattern was demonstrated under lab conditions; it does not show how many layers in a commercial design can use the same approach or what the full process sequence costs.
In other words, fewer exposures are an opportunity, not a guarantee. A layer that does not require the extra resolution may have little reason to switch. Another layer might benefit from fewer patterning operations, but that benefit must be weighed against the scanner’s availability, the process recipe and the integration work required. ASML’s description of reduced double or triple patterning is explicitly a potential benefit, and the actual result is design- and layer-dependent.
The trade-off: finer resolution and a narrower focus window
Higher NA improves resolution, but it reduces depth of focus: the range over which the projected image remains acceptably focused. Imec identifies this as a core process challenge. With a narrower focus window, variations in wafer topography and the behavior of resist—the photosensitive material used to form a pattern—matter more. Focus control and process integration also become more demanding.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesThis is why the scanner’s optical resolution alone cannot predict manufacturing results. A theoretical ability to resolve a smaller pattern does not automatically produce a low-cost layer or a high-yield chip. The pattern must be transferred consistently onto real wafers, in the actual process sequence, with suitable focus and resist control. Imec’s materials discuss these requirements, but the sources cited here do not establish a universal yield advantage for High-NA.
Overlay is another relevant manufacturing measure: it concerns how accurately a new pattern aligns with patterns already present on the wafer. Imec CEO Luc Van den hove characterized the EXE:5200 system’s resolution, overlay performance, throughput and wafer stocker as advantages for accelerating development of sub-2 nm technologies. That statement is imec’s characterization of the system, not an independently established comparison showing superior production results across layers or fabs.
Depth of focus and overlay describe different parts of process control. Depth of focus is about keeping the image acceptably focused on the wafer; overlay is about registering one patterned layer with another. A scanner can have a resolution advantage without that alone resolving every alignment or process-integration challenge. The practical result depends on the whole patterning flow, including how the layer is prepared and how accurately it is positioned relative to existing patterns.
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Imec does not provide a numerical depth-of-focus value in the cited discussion, so the comparison is directional rather than a specific number of nanometers. The safe conclusion is that 0.55 NA narrows the focus window relative to 0.33 NA and therefore raises demands on focus control, resist behavior and wafer topography. It would be misleading to translate that trade-off into a universal yield penalty: the cited material identifies a process challenge, not a quantified production outcome for every design.
Why the equipment itself had to change
Moving from 0.33 to 0.55 NA is not simply a matter of turning a setting up on a conventional EUV scanner. Imec describes High-NA as requiring a new optical design, with mirrors twice as large and ten times heavier as those in the prior generation. The system also uses anamorphic optics, a design choice that is part of the new projection approach.
Those hardware changes help explain why adoption involves more than buying a scanner. Customers and research partners need to develop and qualify compatible processes, establish control of the tighter focus window, and integrate the tool into manufacturing flows. Imec announced that an ASML EXE:5200 arrived at its research facility on March 18, 2026. Research infrastructure is part of this transition alongside work in customer fabs; a system’s presence in a research facility is not itself evidence of broad production deployment.
The larger, heavier mirrors and anamorphic optics are examples of why High-NA represents a platform-level redesign. The advance is not just a software option or a small adjustment to the previous scanner generation. The optical system, wafer handling and process controls all have to support the new imaging approach. Imec CEO Luc Van den hove also highlighted the new wafer stocker in describing the EXE:5200 system, saying it improves process stability and throughput; that remains imec’s characterization rather than a universal production comparison.
There is an ecosystem dimension as well. A research facility can help develop process knowledge and test integration before or alongside customer-fab deployment. Imec’s March 2026 announcement of the EXE:5200’s arrival shows that research infrastructure is part of the transition. It should not be confused with a commercial fab milestone, just as an installation alone does not establish high-volume manufacturing readiness.
Where High-NA is being used
The clearest current production evidence in the cited sources is a selective deployment, not a wholesale shift. On September 7, 2026, Intel Foundry and ASML reported that Intel had processed more than one million wafers across tool certification, research and development, and volume production on select layers for a subset of Core Ultra Series 3 (Panther Lake) processors. The total includes activities beyond volume production. It should not be read as one million commercial chips, one million wafers produced entirely in volume manufacturing, or proof that High-NA patterned every layer in those processors.
Intel also reported that selected 18A layers patterned with High-NA delivered performance meeting or exceeding comparable layers patterned with NXE tools. That is a company-reported result for selected layers. It does not establish that all layers, products or manufacturers will see the same outcome.
This evidence is consistent with selective use: High-NA can be introduced where its resolution and possible reduction in patterning steps justify the process and equipment changes, while conventional EUV remains part of manufacturing. Neither the scanner’s NA nor a chip process label, by itself, tells a reader which layers use which tool.
The “more than one million wafers” figure needs its full scope to be meaningful. Intel Foundry and ASML grouped together tool certification, R&D and volume production on select layers. It is a milestone across these activities, not a count of retail processors or proof that a million wafers went through High-NA volume production alone. Likewise, “select layers” and “a subset” matter: the announcement describes bounded use within a product family, not universal patterning of every layer in every Intel chip.
The reported comparison on selected Intel 18A layers is also narrower than a claim that High-NA is categorically better. Intel said those layers met or exceeded the performance of comparable NXE-patterned layers. That is useful evidence that High-NA can be used on selected production layers, but it does not supply a universal yield, cost or performance result for other layers, products or manufacturers.
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How the adoption timeline has changed
High-NA forecasts should be read with their publication dates and status attached. ASML’s 2024 materials anticipated research and development beginning in 2024–2025 and high-volume manufacturing around 2025–2026. Those were expectations expressed in 2024, not evidence that broad high-volume use began on that schedule.
ASML’s 2025 annual report described the platform as being matured toward high-volume manufacturing requirements by the end of 2026, with customer insertion in 2027–2028. By September 2026, the Intel and ASML milestone documented select-layer volume production for a subset of processors, alongside qualification and R&D activity. A specific customer’s selective production and a supplier’s forecast for broader customer insertion describe different scopes; one does not mean that all leading-edge manufacturers are adopting High-NA on the same timetable.
The dates are not necessarily contradictory because they describe different stages and were published at different times. ASML’s earlier 2025–2026 expectation was a forecast; its 2025 annual report later described maturing the system toward high-volume manufacturing requirements by the end of 2026 and customer insertion in 2027–2028. Intel and ASML’s September 2026 announcement then reported select-layer production for a subset of products, as well as certification and R&D. Read together, these claims point to an evolving transition from development and qualification into limited production, not a single industry-wide launch date.
Nor does customer insertion in 2027–2028 mean that every leading-edge manufacturer will adopt High-NA then. The sources do not establish that all chipmakers will follow the same schedule. Deployment depends on where the finer resolution is useful and whether a manufacturer can qualify and integrate the platform for its own process flow.
What High-NA does—and does not—tell you about a chip
High-NA is a description of lithography optics, not a process node. A node name such as “2 nm” is not a direct measurement of every transistor feature, and ASML’s 8 nm critical-dimension figure for EXE is not a chip’s node name. The figures refer to different things: one is a scanner-related capability, while the other is a process label.
Nor does “High-NA” imply that every layer on a chip was patterned with a 0.55 NA tool. Manufacturing uses different operations and designs across many layers, and Intel’s reported use itself is limited to select layers and a subset of processors. To understand a specific product’s process, the relevant evidence is which layers use which tools and what results are reported for those layers—not the process label alone.
A critical dimension, pitch and process-node label should not be treated as interchangeable. ASML’s 8 nm figure is a quoted EXE critical dimension; imec’s 16 nm-pitch result refers to repeated line-and-space patterns in research images; “2 nm” is an example of a process label. Each figure answers a different question. None, by itself, specifies every physical feature or manufacturing step in a finished chip.
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High-NA is not inherently cheaper just because it may reduce the number of exposures for some patterns. Fewer patterning steps could simplify selected layers, but a meaningful economic comparison would also need to account for tool throughput, masks, yield and process integration. The cited sources establish technical trade-offs and selective use, but do not provide a universal cost-per-layer comparison.
Likewise, the available evidence does not establish a universal yield or throughput advantage over conventional EUV across production layers. Statements by ASML, Intel and imec should be understood in their stated contexts: equipment capability, a research demonstration, a company-reported milestone or an attributed system characterization. They should not be generalized into a guarantee for every product or fab.
Cost depends on more than the number of exposures. A fair layer-level comparison would need to consider the relevant masks and patterning steps, actual tool throughput, yield and integration requirements. If a High-NA exposure replaces multiple steps, that may simplify part of the flow; if it does not, the resolution advantage alone does not establish a cost saving. The cited sources do not provide a universal price-per-layer figure or enough data to calculate one across manufacturers.
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Throughput claims also need context. Imec’s statement about the EXE:5200’s high throughput and wafer stocker is a characterization of the system, while the cited sources do not establish that High-NA has superior production throughput across all layers or fabs. Tool capability, a research demonstration and sustained high-volume fab performance are different kinds of evidence. The same caution applies to yield: a finer image or a successful selected-layer result is not, by itself, proof of a universal yield improvement.
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How to compare the two technologies in practice
For a particular chip layer, the useful question is not simply which scanner has the larger NA. Consider the complete manufacturing trade-off:
- Resolution need: Does the layer contain a pattern for which 0.33 NA requires multiple patterning steps, while 0.55 NA may enable a single exposure?
- Focus and process control: Can the wafer topography, resist and focus-control process support the narrower High-NA depth of focus?
- Layer integration: How does changing the patterning approach affect alignment and the surrounding process sequence?
- Manufacturing economics: Do any avoided exposures outweigh the relevant costs and constraints, including masks, throughput, yield and integration?
- Evidence scope: Is a reported result a research image, qualification activity, select-layer production or broad volume production? These are different milestones.
Without layer-specific design and manufacturing data, there is no sound basis for declaring one technology universally less expensive or better yielding. Conventional EUV and High-NA are best understood as different lithography capabilities that can serve different needs within a manufacturing flow.
That comparison should be made layer by layer rather than by assigning one scanner to an entire process node. First identify the patterning challenge: whether the desired pattern needs the finer resolution and whether conventional EUV would require multiple patterning. Then assess the focus window, resist, wafer topography and overlay requirements. Finally, account for exposures, masks, throughput, yield and process integration. This sequence helps separate a genuine manufacturing advantage from a headline specification.
It also helps avoid common misreadings. An 8 nm critical dimension is not a “2 nm” node; a 16 nm-pitch lab image is not a production-yield result; and a million-wafer milestone spanning certification, R&D and selected-layer volume production is not a million commercial chips. The meaningful comparison is what each scanner can do on a specified layer in a qualified manufacturing flow.
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Does High-NA EUV use a different wavelength?
No. Conventional EUV and High-NA EUV both use 13.5 nm light. High-NA refers to the projection optics: ASML’s NXE tools use 0.33 NA and its EXE tools use 0.55 NA.
Is High-NA EUV always better than conventional EUV?
No single scanner is best for every layer or manufacturing flow. High-NA can resolve finer images and may let some patterns use fewer exposures, but it also reduces depth of focus and requires demanding process control. The benefit depends on the layer and on the complete process integration.
Does High-NA mean a chip is made on a 2 nm process?
No. High-NA describes a scanner’s optical system, not a process-node label. ASML’s 8 nm critical-dimension figure for EXE is a scanner capability, while a label such as “2 nm” is not a direct measurement of every feature on a chip.
Does High-NA make chip production cheaper?
Not automatically. It may reduce double or triple patterning on selected layers, but a cost comparison also needs to account for masks, exposure count, throughput, yield and process integration. ASML’s 2024 materials describe fewer patterning steps as a potential benefit, and the cited sources do not give a universal cost-per-layer comparison.
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What does Intel’s one-million-wafer milestone mean?
Intel Foundry and ASML reported in September 2026 that more than one million wafers had been processed across tool certification, R&D and volume production on select layers for a subset of Core Ultra Series 3 (Panther Lake) processors. The figure is not one million commercial chips or one million wafers processed entirely in volume production.
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Has High-NA replaced conventional EUV in chip manufacturing?
No. By September 2026, Intel and ASML had reported selective production use alongside research and qualification activity. The report concerns selected layers and a subset of processors, not broad replacement of conventional EUV across the industry.
What is the practical meaning of the narrower depth of focus?
It means the acceptable focus range is reduced relative to 0.33 NA, making wafer topography, resist behavior and focus control more important. Imec identifies this as a process challenge but does not state a universal numerical depth-of-focus value or a universal yield effect.
Frequently Asked Questions
Does High-NA EUV use a different wavelength?
No. Both conventional and High-NA EUV use 13.5 nm light; the change is from 0.33 NA on ASML NXE systems to 0.55 NA on EXE systems.
Is High-NA EUV always better than conventional EUV?
No. It can resolve finer patterns and may reduce exposures on selected layers, but it also narrows depth of focus and raises process-control demands. The benefit depends on the particular layer and manufacturing flow.
Does High-NA mean a chip is made on a 2 nm process?
No. High-NA describes lithography optics, not a process node. ASML’s 8 nm EXE critical-dimension figure is a scanner capability, not a node label or a measurement of every chip feature.
Does High-NA EUV make chip production cheaper?
Not automatically. Fewer exposures may help on selected layers, but total economics also depend on masks, throughput, yield and process integration. The cited sources do not give a universal cost-per-layer comparison.
What did Intel’s one-million-wafer milestone cover?
Intel Foundry and ASML reported in September 2026 that more than one million wafers had been processed across certification, R&D and volume production on select layers for a subset of Core Ultra Series 3 processors. It is not a count of commercial chips or volume-production wafers alone.
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Has High-NA replaced conventional EUV?
No. The September 2026 production report describes selective use on certain layers and products, alongside qualification and R&D—not broad replacement across chip manufacturing.
The Bottom Line
High-NA EUV keeps 13.5 nm light but raises numerical aperture from 0.33 to 0.55, enabling finer imaging and potentially fewer patterning exposures on selected layers. The trade-off is a narrower focus window, a redesigned optical platform and demanding integration work. Intel and ASML reported selective production use by September 2026, but High-NA is not a universal replacement for conventional EUV—and the cited sources do not establish a universal cost, yield or throughput advantage.
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