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Dual-ported RAM is memory with two access ports that can reach the same memory array at the same time. The two ports give separate logic paths or agents access to a shared memory space, but the term alone does not say whether both ports can write or how simultaneous accesses to the same address behave.

What dual-ported RAM means

A port is an access interface to memory: it provides the signals needed to select an address and read data, write data, or both. Dual-ported RAM has two such interfaces connected to one shared memory array, so two access paths can operate concurrently, subject to the memory’s supported configuration.

“Dual-port” describes the number of access ports, not a universal set of capabilities. A design may dedicate one port to reading and the other to writing, or it may allow each port to read and write. Vendor documents also use the terms simple dual-port RAM and true dual-port RAM for these different arrangements.

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Simple dual-port RAM versus true dual-port RAM

In Intel’s terminology, simple dual-port mode assigns a dedicated port to each read and write operation. True dual-port mode provides two ports, each of which can perform reads or writes. The precise port signals and supported combinations remain specific to the device or memory primitive.

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Configuration Operations per port Addresses Clocking and collisions
Simple dual-port A dedicated read port and a dedicated write port in Intel’s documented arrangement. Separate address ports for the read and write operations. Clocking and same-address read/write results depend on the selected memory implementation and configuration.
True dual-port Each port can perform reads or writes, as described in Intel’s parameterizable macro documentation. Two address ports; each port supplies its own address. Clocking and collision results depend on the selected memory implementation and configuration. Simultaneous writes to the same address can be indeterminate.

Intel’s macro documentation describes the distinction in its simple dual-port port descriptions and true dual-port macro guide. These names should be read in the context of the relevant vendor documentation rather than assumed to define every memory product identically.

What concurrent access does—and does not—guarantee

Two ports allow overlapping memory operations; they do not guarantee a predictable outcome for every combination. The most important hazard is a collision: both ports access the same address at overlapping times. In particular, Altera’s Quartus Prime Pro Edition 25.1 documentation says that simultaneous writes to the same location on both ports produce indeterminate behavior. Intel’s embedded-peripheral guide also documents undefined results for simultaneous same-address access in its described configuration.

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Read-during-write behavior is another implementation-specific detail. Depending on the memory primitive and configuration, a read that overlaps a write may have rules different from a write/write collision. Do not assume a universal outcome; check the target memory’s documentation. See Altera’s true dual-port synchronous RAM guide and Intel’s embedded-peripherals memory type documentation for the limits of the configurations they describe.

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Where FPGA dual-port RAM can be implemented

In an FPGA design, dual-port RAM may map to different on-chip memory resources. AMD’s Vitis Model Composer documentation identifies distributed memory, block RAM, and UltraRAM as possible implementation resources, where supported by the target device. These are implementation choices; they are not part of the general definition of dual-ported RAM. See AMD’s Dual Port RAM documentation.

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What to verify before using it

  • Whether each port can read, write, or both, and which combinations are supported.
  • Whether the ports share a clock or can use separate clocks, and what timing rules apply.
  • What happens when both ports access the same address, including simultaneous writes and read-during-write cases.
  • Which memory resource the design uses and whether the target device supports it.

Check the target device’s memory documentation and the specific primitive or macro configuration. For example, AMD’s 7-series BRAM_TDP_MACRO documentation applies to that macro and guide version; behavior should not be generalized to other devices or vendors without checking their documentation.

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