iTechGuides is reader-supported. When you buy through links on our site, we may earn an affiliate commission. As an Amazon Associate I earn from qualifying purchases. Learn more
Short answer: A Wccftech report dated October 14, 2026, says a semiconductor expert used Meta’s Muse personal AI agent to design and test a cryptocurrency-focused system-on-chip (SoC) based on RISC-V, then run software used in manufacturing preparation, for about $2,000. That is a reported experiment, not independently verified proof of a fabricated chip, working silicon, or a blockchain that is actually “the fastest on Earth.”
What the October 14 report actually claims
Wccftech describes an end-to-end design exercise aimed at the Thru blockchain. According to the report, Muse was used across several stages:
- Creating a crypto-specific SoC design around the RISC-V instruction-set architecture.
- Testing the design in software.
- Running tools associated with preparing a design for manufacturing.
- Completing the work at an estimated cost of roughly $2,000.
The project’s stated ambition was to make Thru “the fastest on Earth.” That phrase belongs to the report or the project’s objective; it is not an independently measured throughput result. The available account does not publish the chip’s microarchitecture, RTL source, clock rate, process node, area, power, tape-out record, silicon part number, or reproducible benchmark.
The Tool Desk
Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →What Muse is—and what Meta has not claimed
Meta’s official product description calls Muse “Your personal AI agent that gets things done.” Meta says the agent can answer questions, complete tasks, browse the web, make purchases, generate images, create documents, connect to apps, set reminders, monitor goals, continue working in the background, and build a tool when a required tool does not exist.
#1 Best Overall
- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Those capabilities support the idea that Muse could coordinate a long, tool-heavy workflow. They do not establish that Muse is a dedicated electronic-design-automation (EDA) system or that Meta has released a chip-design product. The reported SoC work would therefore be an application of a general agent to an engineering process, rather than a documented Meta chip-design platform.
Why RISC-V matters in a blockchain-oriented SoC
RISC-V is an open instruction-set architecture. A chip designer can implement a RISC-V CPU core and add domain-specific hardware, such as cryptographic engines, without adopting a proprietary CPU instruction set. In a blockchain accelerator, that could mean combining general-purpose control software with fixed-function or customized units for hashing, signatures, elliptic-curve operations, transaction validation, or data movement.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
That is the architectural role RISC-V plays in the report: it is the selected CPU instruction set for the alleged Thru SoC. No public specification shows which RISC-V profile, extensions, accelerator interfaces, memory system, or cryptographic algorithms the specific chip uses. Those details should not be inferred from the headline.
Recommended Free Tools
Evidence levels: design files are not working silicon
Chip projects produce artifacts at progressively stronger levels of evidence. The reported work should be judged against that ladder:
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
| Evidence level | What it can show | What it cannot prove by itself |
|---|---|---|
| Generated RTL or hardware description | A proposed digital circuit and its interfaces | That the logic is bug-free, manufacturable, or fast enough |
| Simulation and compliance tests | Behavior under the tested models and test cases | Physical timing, power, yield, or real-world throughput |
| Place-and-route output or GDS | A physical layout prepared for a specified manufacturing flow | That a wafer was ordered, fabricated, or electrically functional |
| Tape-out and fabrication | Submission to a foundry and production of manufactured dies | That the first silicon works to specification |
| Bring-up and independent benchmarks | Measured operation, performance, power, and reliability on hardware | Nothing beyond the tested conditions; broader claims still need comparable measurements |
The Wccftech account does not independently establish the last two levels for the Thru project. In particular, “manufacturing preparation” should not be read as confirmation that the design reached a foundry.
What the separate museRISC project demonstrates
A public GitHub project named museRISC provides useful context, but it is not evidence that the reported Thru SoC exists. Its README describes an open RV64 RISC-V processor with a crypto accelerator and documents:
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
- RTL for SHA-256, SHA-512, Keccak-f1600, and elliptic-curve arithmetic.
- Verilator-based simulation.
- RISC-V compliance testing.
- Booting Linux 6.6 in a platform model.
- An OpenROAD-generated GDS for a standalone cryptographic macro.
The same README says the cryptographic macro is not attached to the processor core and that the project has not been taped out. It also warns that completing place-and-route and generating GDS do not equal fabrication or silicon verification. Those qualifications make museRISC a demonstration of substantial RTL- and simulation-level work, not a working blockchain chip.
Does $2,000 make an SoC plausible?
It can be plausible as a reported out-of-pocket cost for an experiment that relies heavily on open-source software, automated agents, existing compute, and a limited prototype scope. It is not a complete cost model for commercial silicon.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
The report gives no itemized breakdown, so readers cannot tell how much covered cloud compute, engineering labor, EDA access, design revisions, verification, prototype boards, or foundry fees. It also does not state whether the figure is a one-time estimate, which country’s prices it reflects, or whether any manufacturing payment was included. A $2,000 design exercise and a $2,000 fabricated production chip are radically different claims.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Is Thru really the fastest blockchain?
Nothing in the available reporting independently verifies that. “The fastest on Earth” is presented as the project’s goal or promotional claim. A credible comparison would need a defined workload, transaction and block-size assumptions, confirmation rules, hardware and software versions, sustained throughput, latency, and energy measurements, with results reproduced by an independent party.
Without those measurements, the chip’s alleged design success and the blockchain’s alleged speed remain separate questions. Even a functioning accelerator would not automatically make an entire blockchain fastest: consensus, networking, storage, software implementation, and adoption can all limit end-to-end performance.
Do these 3 things before closing this tab:
1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesHow to read the claim responsibly
- Attribute the $2,000 figure and workflow claim. They come from Wccftech’s October 14, 2026 report.
- Treat Muse’s role as agent orchestration. Meta documents a general-purpose personal agent, not a specialized EDA product.
- Ask for primary artifacts. A public RTL repository, test logs, architecture specification, and reproducible build would make the design easier to evaluate.
- Look for physical proof. Tape-out documents, packaged dies, board bring-up results, and independent electrical measurements are required to establish working silicon.
- Separate blockchain benchmarks from chip claims. Thru’s performance needs independently reproducible network measurements rather than a project slogan.
Bottom line
The story is best understood as an ambitious demonstration of what an AI agent may coordinate in a RISC-V chip-design workflow for a relatively small reported budget. It is not yet a verified account of a manufactured crypto SoC, and it does not prove that Thru is the world’s fastest blockchain. The separate museRISC project shows that open RISC-V crypto hardware can reach detailed simulation and layout stages while still falling short of tape-out and silicon.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
