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To optimize an LLM with CUDA or ROCm/HIP, start by measuring a representative workload, identify whether its limit is compute, memory, data transfer, or scheduling, then change one relevant layer and measure again. The best approach depends on the model, GPU, runtime, and whether you are training, processing prompts, or generating tokens; there is no established universal winner between the two stacks.
Define the workload before tuning
Optimization only makes sense against a goal. Before profiling, write down what the application must do and what a successful result means. A single interactive request with a strict latency target is different from a serving system trying to maximize tokens per second across many concurrent requests.
- Task: training, fine-tuning, or inference.
- Model and checkpoint: record the exact model and revision you are running.
- Input and output: use realistic prompt lengths and generated-token counts, including the range you expect in production.
- Traffic: note batch size, concurrency, and whether requests arrive together or over time.
- Success metric: choose the relevant measure, such as request latency, prefill latency, decode throughput, or total throughput.
- Environment: record the GPU, memory capacity, framework, runtime, kernel libraries, and software versions.
These details make the result interpretable and give you a repeatable baseline. A test with short prompts and one request may point to different bottlenecks from a live service processing long contexts at high concurrency.
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Profile before changing kernels or runtime settings. NVIDIA’s CUDA C++ Best Practices Guide 13.0 recommends profiling realistic workloads to locate hotspots; a synthetic or unrepresentative test can direct effort toward code that is not important in actual use.
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On NVIDIA, use the profiling approach supported by your CUDA environment to determine where time is spent across CPU work, GPU kernels, memory activity, and host-device transfers. On AMD, the ROCm programming documentation identifies rocprofv3, ROCm Compute Profiler, and ROCm Systems Profiler as candidate profiling tools. Check the documentation for your installed ROCm release before relying on a particular tool or invocation.
Classify the dominant issue before optimizing:
- Compute-bound: the work is limited mainly by arithmetic throughput or insufficient parallel work.
- Memory-bound: data movement or memory bandwidth limits progress, even if the GPU has unused arithmetic capacity.
- Transfer-bound: host-device movement or many small transfers consume meaningful time.
- Scheduling- or CPU-bound: launch overhead, request handling, synchronization, or other CPU work prevents the GPU from staying productively occupied.
These categories can overlap. Measure the workload rather than assuming its matrix multiplications are the bottleneck.
Separate prompt processing from token generation
Inference has distinct phases that can have different performance limits. NVIDIA’s November 17, 2023 article on inference optimization describes prefill as processing the known input tokens in parallel and computing intermediate key/value states. Decode then generates output tokens autoregressively, using those states as it produces each next token.
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| Phase | What it does | What to measure | Optimization question |
|---|---|---|---|
| Prefill | Processes the prompt and computes key/value states. | Prompt-processing latency and GPU utilization for the target prompt lengths. | Is the prompt workload exposing enough parallel work, and is computation or memory limiting it? |
| Decode | Generates output tokens one at a time. | Decode throughput and latency under the target output lengths and concurrency. | Is token generation limited by moving model weights or KV-cache data, or by scheduling and utilization? |
The NVIDIA article characterizes decode as memory-bound in the setting it discusses, not as a rule for every model or deployment. Profile each phase in your own workload; an aggregate request-time number can hide which phase needs attention. See NVIDIA’s inference optimization overview for the phase distinction and the serving techniques discussed there.
Choose an optimization that matches the bottleneck
CUDA and ROCm/HIP differ in APIs, hardware, and software support, but many performance principles overlap. NVIDIA’s CUDA guide emphasizes parallel execution, memory bandwidth, and instruction usage. AMD’s HIP 7.15.0 performance guidelines likewise cover transfers, occupancy, coalesced access, and on-chip data reuse. Apply the specific guidance only after confirming it fits your GPU and software release.
| Observed limit | Potential change | What to verify |
|---|---|---|
| Too little parallel work or poor GPU utilization | Expose more independent work or adjust the execution strategy to keep the GPU occupied. | Check whether utilization improves without creating a memory-capacity problem or raising latency for the target workload. |
| Host-device transfer overhead | Reduce unnecessary transfers and combine small transfers where appropriate. | Confirm transfer time falls and that the new data path preserves correctness. |
| Inefficient global-memory access | Coalesce global loads and stores where the data layout and kernel permit. | Re-profile memory behavior; coalescing is a kernel-level opportunity, not a guarantee of end-to-end improvement. |
| Repeated access to reusable data | Consider on-chip reuse, using the relevant hardware mechanism such as shared memory or AMD LDS. | Check resource use and occupancy; keeping more data on-chip can compete with other resource needs. |
| Matrix or tensor operation efficiency | Evaluate supported data types and dimension alignment for the target hardware and library. | Validate numerical accuracy and measure the actual operation. NVIDIA documents different alignment conditions for TF32, FP16, and INT8; no single rule applies to every GPU generation or library version. |
NVIDIA’s deep-learning performance guidance explains how data type and dimension alignment affect Tensor Core efficiency. Treat alignment as a hardware- and operation-specific consideration, not a universal requirement. For AMD, consult the documentation for the ROCm version and GPU in use rather than assuming an NVIDIA-specific behavior maps directly to HIP.
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Treat inference features as system-level choices
For serving workloads, runtime features can change memory use, throughput, and latency together. The 2023 NVIDIA inference article discusses batching, KV-cache management, grouped-query and multi-query attention, FlashAttention, PagedAttention, quantization, and in-flight batching. These are avenues to evaluate, not guaranteed wins: framework availability and behavior depend on the current software stack, model, hardware, and traffic pattern.
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Batching can improve GPU utilization by processing work from multiple requests together. But a static batch can be delayed by requests that generate more tokens, and larger batches consume more memory. Test realistic request lengths and concurrency, and assess both throughput and the latency experienced by individual requests.
KV cache and attention
The KV cache stores intermediate attention data used during generation, so its memory demand matters as context and concurrency grow. Attention implementations and cache-management strategies can affect the balance between memory capacity, data movement, and throughput. Measure peak and steady-state memory use as well as speed when evaluating a change.
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Quantization
Quantization can reduce the memory required for model weights and may alter inference performance, but lower precision can affect output quality and kernel support varies. Validate the chosen model and configuration against task-relevant quality checks rather than treating memory savings as proof of an acceptable result.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Keep CUDA and ROCm comparisons like-for-like
A platform comparison is meaningful only when the workload and measurement conditions match. Record the same model checkpoint, numerical precision, prompt and output lengths, batch size, concurrency, and measurement method for both runs. Also record each GPU’s model and memory capacity, along with framework, runtime, kernel, and driver versions.
Report prefill latency separately from decode throughput when those phases matter to the use case. Include peak and steady-state memory use, and state whether measurements are for a single request or a serving workload. Do not present results from different models, input lengths, software versions, or hardware as a CUDA-versus-ROCm head-to-head. The available sources establish no directly comparable current CUDA-versus-ROCm LLM benchmark figure.
Software compatibility is version-specific. NVIDIA’s TensorRT-LLM documentation links to release notes and a support matrix; check those for the combination you intend to use. AMD’s versioned ROCm 6.2.0 LLM fine-tuning and inference optimization page is not enough to establish a current GPU or framework support matrix. Confirm support in current versioned documentation before choosing a stack or assuming a particular framework feature is available.
Remeasure and preserve correctness
- Save the baseline profile and record the workload, hardware, and software versions.
- Choose one change that addresses the measured limit, rather than stacking several speculative changes.
- Run the same workload with the same measurement procedure and compare the same metrics.
- Report absolute results as well as relative change, with the conditions that produced them.
- Run correctness checks for training or inference and quality checks for any precision or quantization change.
If a change does not improve the target metric, or causes a quality, memory, or latency regression elsewhere, revert it or test a different layer. Keep optimizations that improve the objective under the actual operating conditions—not merely a narrow synthetic benchmark.
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