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There is no single drop-in replacement for HBM. The practical approach is to match each workload’s memory tier to its bottleneck: LPDDR5X or DDR5 when capacity, power, cost, or serviceability matter most; CXL when memory must be attached or pooled; coherent CPU-plus-accelerator designs when a large shared address space is valuable; and on-chip SRAM, Block RAM, or UltraRAM when keeping hot data close to compute can reduce external traffic. GDDR is another candidate, but its suitability depends on the specific accelerator and memory-controller design.
All of these options trade away some of HBM’s local bandwidth or latency. Choose with sustained application measurements—not peak GB/s alone—and keep the hottest tensors in the fastest tier available.
Why HBM alternatives require a workload-first decision
High-bandwidth memory (HBM) places wide, fast memory close to an accelerator. That arrangement is valuable when a kernel repeatedly streams large tensors and cannot reuse data from a smaller cache. It is not automatically the best answer for every memory-intensive system: HBM-equipped packages can cost more per gigabyte, offer less total capacity than a larger external-memory design, and be difficult to service or expand.
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Memory-intensive AI also has several different traffic patterns. Training must hold parameters, gradients, activations, optimizer state, and often checkpoints. Autoregressive inference has a large prefill phase and a decode phase dominated by key-value (KV) cache reads and writes. Data preparation may need capacity for large batches while tolerating higher latency. An alternative that works for one phase can be a bottleneck in another.
Comparison of the main alternatives
| Memory approach | What it changes | Documented figures or limits | Best fit | Main trade-off |
|---|---|---|---|---|
| LPDDR5X capacity-first platform | Large, efficient memory integrated with the CPU or system package | Up to 960 GB and up to 500 GB/s on the Grace CPU Superchip, at about 16 W, according to NVIDIA’s Grace Performance Tuning Guide | Large models, inference, and preprocessing where capacity and energy are more important than maximum local bandwidth | Integrated memory is not normally field-replaceable; topology and NUMA placement affect performance |
| External DDR5 | High-capacity, socketed memory connected through conventional channels | AMD’s cited Alveo example reports 77 GB/s for DDR-based cards | Capacity-heavy workloads, FPGA designs with tiling, and systems prioritizing cost or serviceability | Much lower bandwidth than the cited HBM implementation; channel and bank placement are critical |
| CXL-attached or pooled memory | Adds or shares memory over a cache-coherent expansion fabric | AMD lists CXL cache-coherent interfaces; no universal bandwidth or end-to-end AI result is established | Disaggregated capacity, weight storage, optimizer state, checkpoint staging, and multi-device sharing | Extra latency, protocol and topology dependencies, and possible fabric contention |
| Coherent CPU-plus-accelerator design | Lets the accelerator address a large CPU memory pool through a high-speed coherent link | Grace Hopper documentation cites up to 900 GB/s total NVLink-C2C bandwidth and up to 512 GB of directly accessible LPDDR5X CPU memory in the described configuration | Working sets larger than local accelerator memory and software that benefits from shared pointers | Platform-specific programming and nonuniform latency between local and host memory |
| On-chip SRAM, Block RAM, or UltraRAM | Keeps frequently reused tiles, coefficients, and buffers inside the device | AMD describes distributed RAM, Block RAM, and UltraRAM as internal storage choices | Regular FPGA or adaptive-SoC pipelines with predictable reuse | Capacity is far below external DRAM; these memories complement rather than replace model storage |
| GDDR | Uses graphics-oriented DRAM with multiple channels on an accelerator card | No current, vendor-neutral AI benchmark is established by the cited material | Inference or graphics-derived accelerators with sufficient channels and capacity | Results vary by controller, channel count, capacity, and software; measure the target card |
LPDDR5X: the capacity and efficiency option
LPDDR5X is attractive when the system needs a large memory pool without the power and cost of a very wide HBM stack. NVIDIA’s Grace CPU Superchip is documented with up to 960 GB of LPDDR5X and up to 500 GB/s of bandwidth at about 16 W. The memory is server-class, includes error-correcting code (ECC), and is integrated into a compact co-packaged design.
In the same comparison, NVIDIA says the cited HBM2e subsystem costs more than three times as much per gigabyte and has one-eighth the maximum capacity of the LPDDR5X configuration. Those figures describe that specific subsystem comparison, not every HBM or LPDDR5X product.
When LPDDR5X is a strong fit
- Large model weights: The capacity can keep a model resident instead of repeatedly fetching portions from slower storage.
- Inference fleets: Lower memory power can improve rack-level efficiency, especially when arithmetic utilization is modest.
- Data-heavy preprocessing: Tokenization, feature assembly, and staging can use a large pool without requiring HBM-class local bandwidth.
- Capacity-first HPC: Applications with moderate bandwidth demand can gain from capacity and power efficiency.
What to check before choosing it
- Confirm the exact memory topology and which processor or accelerator can access each region directly.
- Follow the platform’s NUMA and placement guidance; a remote LPDDR5X access can behave differently from local access.
- Verify that the integrated memory capacity is sufficient for model, KV cache, optimizer, and checkpoint requirements at the intended batch size.
- Plan for the fact that integrated memory is generally not replaceable like a DDR5 DIMM.
DDR5: high capacity, broad sourcing, and serviceability
DDR5 remains the most straightforward way to add large, replaceable memory modules to a server or accelerator host. AMD documents DDR5 and DDR4 interfaces, along with LPDDR5/5X, RLDRAM3, and QDRIV options, for accelerator-oriented adaptive SoCs and FPGAs. This breadth allows designers to select capacity, endurance, packaging, and sourcing characteristics independently of the compute die.
DDR5 is not a bandwidth-equivalent substitute for HBM. AMD’s Vitis Tutorials 2024.2 documentation describes memory-bound algorithms limited by 77 GB/s on DDR-based Alveo cards. The cited HBM implementation is described at up to 460 GB/s theoretical bandwidth and about 420 GB/s achievable bandwidth. These values show the order-of-magnitude trade-off for that example; they are not a guarantee for every card or kernel.
Where DDR5 works well
- Capacity-dominated inference: Keep weights and large KV caches in DDR5 when token latency targets tolerate the lower bandwidth.
- FPGA pipelines with tiling: Stream blocks through on-chip buffers so each DDR5 fetch is reused several times.
- Training support memory: Hold optimizer state, checkpoints, or less frequently accessed tensors outside the hottest path.
- Serviceable systems: Replace or expand modules without replacing the accelerator package, subject to platform limits.
How to avoid common DDR5 bottlenecks
- Use all available channels and balance capacity across them; a single populated channel can leave theoretical bandwidth unused.
- Keep producer and consumer data on the same NUMA node where possible.
- Align allocations with the accelerator’s banks and burst requirements.
- Tile, batch, compress, or quantize data so each transfer does more useful work.
- Measure sustained bandwidth under the real kernel mix rather than relying on a memory-module specification.
CXL memory expansion and pooling
Compute Express Link (CXL) provides cache-coherent connections for attaching memory near a CPU or accelerator. AMD explicitly lists CXL among the cache-coherent interfaces supported by its accelerator-oriented devices. A CXL memory expander can add capacity without placing every byte on the accelerator package; a pooled design can let multiple compute devices draw from a shared resource.
Good CXL use cases
- Large, mostly read-only model weights shared by several accelerators.
- Optimizer state or activation storage that exceeds local memory but is accessed less frequently.
- Checkpoint staging and recovery buffers.
- Disaggregated servers in which memory capacity must be allocated independently of compute cards.
Compatibility requirements
- Confirm that the CPU, accelerator, root complex, and CXL memory device support the same CXL generation and required protocol mode.
- Check firmware support for memory discovery, error handling, and address interleaving.
- Verify operating-system and driver support for the intended memory semantics and NUMA exposure.
- Map which allocations are local, CXL-attached, or pooled, and expose that distinction to the runtime.
- Benchmark contention when several devices access the same link or switch.
CXL adds a path, not free bandwidth. The cited material does not establish a universal CXL bandwidth number or an end-to-end AI benchmark, so results must be measured on the exact generation, switch topology, device count, and software stack. Treat CXL memory as a slower tier unless testing proves otherwise.
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Coherent CPU-plus-accelerator systems
A coherent design can extend an accelerator’s usable address space without requiring every tensor to be copied explicitly between separate memories. NVIDIA’s Grace Hopper description gives an example: a Hopper GPU and Grace CPU communicate through NVLink-C2C with up to 900 GB/s total bandwidth, and the GPU can directly address up to 512 GB of the CPU’s LPDDR5X memory in the cited configuration.
Why coherence can simplify large workloads
- Shared pointers reduce explicit page migration and duplicate buffering.
- CPU and accelerator code can operate on a common allocation while retaining separate local-memory tiers.
- Large weights or KV-cache segments can remain in CPU memory until they are needed.
- Irregular algorithms can avoid the rigid staging schedule required by a purely discrete design.
Important limitations
Directly addressable host memory is not equivalent to local HBM. Local accelerator memory normally has lower latency and a different sustained bandwidth profile. A kernel that repeatedly reads remote LPDDR5X can still stall, even when the link itself is fast. Use the coherent region for capacity and less-hot data, and place bandwidth-critical tiles in local memory. The programming model, compiler behavior, and page-placement controls are also platform-specific.
On-chip SRAM, Block RAM, and UltraRAM
Internal memory is the most effective complement when the same values are reused many times. AMD distinguishes distributed RAM, Block RAM, and UltraRAM for accelerator-oriented devices. Designers can use these resources for coefficients, line buffers, lookup tables, FIFOs, and tiled tensor blocks.
Patterns that benefit
- Convolution windows that reuse neighboring pixels or activations.
- Matrix tiles sized to fit an on-chip buffer, reducing repeated external reads.
- Quantization tables and small embedding fragments accessed by every pipeline stage.
- Streaming transforms with deterministic producer and consumer rates.
Internal RAM cannot hold a modern model’s full weights or a large inference KV cache. Its role is to reduce traffic to DDR, LPDDR5X, GDDR, CXL, or HBM by increasing reuse. Capacity planning should reserve enough blocks for buffering and synchronization rather than treating every bit as tensor storage.
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GDDR can provide substantial capacity and bandwidth on an accelerator card, particularly for inference designs derived from graphics hardware. Its usefulness depends on the number of channels, controller efficiency, memory clock, capacity per device, and the way software schedules accesses.
The available official material establishes the DDR-versus-HBM trade-off but does not provide a current, vendor-neutral GDDR AI benchmark or product comparison. Do not assume that a GDDR card will match HBM, or that every GDDR implementation is interchangeable. Request sustained bandwidth, latency, capacity, and power results for the exact accelerator and target kernels.
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Match the memory tier to the AI workload
Training
Training often needs parameters, gradients, activations, and optimizer state simultaneously. Keep frequently reused weights and activations in the fastest local memory. Use LPDDR5X, DDR5, or CXL for capacity overflow, optimizer state, and checkpoint staging when the training algorithm can tolerate additional latency. Measure the effect of gradient accumulation and recomputation, since both change memory traffic as well as capacity.
Autoregressive inference
Separate prefill from decode in every test. Prefill processes a long prompt and can have substantial matrix-multiplication throughput. Decode handles one or a few new tokens at a time and is often constrained by KV-cache traffic and memory latency. A capacity-first tier can hold more concurrent sessions, but a lower-bandwidth tier may reduce tokens per second during decode. Record both throughput and per-token latency at the intended concurrency.
Data preparation and retrieval
Tokenization, feature extraction, retrieval, and post-processing frequently benefit from capacity and host-side access more than from HBM-class bandwidth. LPDDR5X or DDR5 can keep large working sets close to the CPU, while CXL can provide expandable staging space. Use on-chip buffers only for the small, repeatedly accessed structures in the accelerator pipeline.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.A practical selection procedure
- Inventory the working set. Calculate resident model weights, activations, gradients, optimizer state, KV cache per session, checkpoint buffers, and framework overhead. Record peak and steady-state sizes separately.
- Classify each tensor by heat. Mark data as hot (streamed or reused every kernel), warm (periodically accessed), or cold (checkpointed or rarely read). Hot data should remain in local accelerator memory or on-chip RAM whenever possible.
- Measure the current kernel mix. Capture sustained read and write bandwidth, achieved occupancy, cache hit rates, stall reasons, batch size, sequence length, and concurrency. A single synthetic copy test is not enough.
- Select a capacity tier. Use LPDDR5X or DDR5 for a large local pool, CXL for attachable or shared capacity, or a coherent CPU-plus-accelerator platform when a unified address space reduces software complexity.
- Design the data path. Define placement, prefetching, tiling, compression, quantization, and eviction rules. Document which allocations can spill and what latency is acceptable.
- Prototype the worst case. Test the largest model, longest sequence, highest session count, and checkpoint or recovery operation—not only the median request.
- Validate operations. Check ECC behavior, replacement procedures, firmware updates, thermal limits, and how a failed memory device affects service.
Benchmarking: numbers that predict production behavior
Use sustained application bandwidth as the primary comparison. Report effective GB/s for the actual tensor sizes and access pattern, not just the vendor’s peak specification. Include latency percentiles, energy per byte, usable capacity after reservations, and software overhead.
| Measurement | Why it matters | How to report it |
|---|---|---|
| Kernel bandwidth | Shows whether the selected tier feeds the real operation | Read and write GB/s for representative training, prefill, and decode kernels |
| Capacity headroom | Prevents paging or out-of-memory failures at peak load | Usable bytes after runtime reservations, with model, sequence, and batch dimensions |
| Latency and tail latency | Remote or pooled memory can hurt responsiveness even when average throughput is acceptable | Median and high-percentile access or token latency by memory tier |
| Energy per byte | Memory power can dominate a dense AI server | Memory joules per transferred byte under the target workload |
| Scale-out behavior | Links and switches can contend as device count grows | Throughput and latency with one device, full rack configuration, and failure scenarios |
| Software portability | Placement APIs and coherent pointers may be platform-specific | Code changes, supported runtimes, and fallback behavior when a tier is unavailable |
Common failure modes and fixes
Buying more compute for a memory-bound kernel
If profiling shows time spent waiting for loads and stores, a larger arithmetic engine will not solve the limit. Increase effective reuse, improve placement, add channels, or move hot data to a faster tier.
Treating peak bandwidth as sustained bandwidth
Peak figures assume ideal access, full channel utilization, and no contention. Bank conflicts, unbalanced channels, small transfers, synchronization, and competing tenants can reduce delivered bandwidth. Use the production kernel mix in the benchmark.
Spilling without a placement policy
Automatic overflow can move a hot tensor to DDR5 or CXL and create unpredictable stalls. Define explicit hot, warm, and cold regions, then monitor migration and page faults.
Ignoring NUMA and fabric topology
A CPU, accelerator, CXL device, and switch may not be equally distant. Pin threads and allocations to the appropriate NUMA node, and test traffic across every link that production will use.
Underestimating inference KV-cache growth
KV cache scales with sequence length, layers, hidden size, precision, and concurrent sessions. Capacity planning based only on model weights can fail during long-context or high-concurrency serving.
Assuming coherent access removes all copies and costs
Coherence simplifies addressing, but remote memory still has latency and bandwidth characteristics. Keep hot tiles local and verify that compiler and runtime placement match the intended design.
Cost, power, and serviceability trade-offs
Compare total cost per usable gigabyte, not package price alone. Include memory power, cooling, host slots, accelerator utilization, software engineering, and the cost of replacing or expanding the system. LPDDR5X can reduce power and, in NVIDIA’s cited Grace comparison, cost per gigabyte relative to the specific HBM2e subsystem. DDR5 generally offers the easiest field replacement and broadest sourcing. CXL can let operators add capacity independently of compute, but switches, memory devices, and validation add platform cost. On-chip RAM consumes scarce device resources but can lower external traffic enough to improve energy per inference.
Serviceability also affects availability. Socketed DDR5 and external CXL devices can be replaced or expanded under a defined maintenance process. Integrated LPDDR5X and HBM packages require platform-level replacement. Document ECC coverage, spare capacity, firmware recovery, and the behavior of a failed memory link before standardizing a design.
Decision rules
- Capacity is the bottleneck: Start with LPDDR5X, DDR5, or a CXL capacity tier, then measure spillover traffic.
- Sustained bandwidth is the bottleneck: Keep the hottest tensors in local fast memory; apply tiling, compression, batching, quantization, and locality-aware placement before accepting a lower-bandwidth accelerator.
- A unified address space is the priority: Evaluate a coherent CPU-plus-accelerator platform and test remote-memory latency separately from local-memory latency.
- The workload is stable and structured: Combine FPGA on-chip RAM with banked external DDR5 and design the pipeline around reuse.
- The candidate is GDDR: Require measurements for the exact card, controller, capacity, and kernel mix because no vendor-neutral result establishes a universal ranking.
- The system will scale out: Include fabric contention, topology, power, and failure recovery in the benchmark rather than comparing isolated cards.
The best alternative to an HBM-equipped accelerator is therefore a memory hierarchy matched to the workload: fast local storage for hot data, a capacity tier for the rest, and a measured path between them. Treat LPDDR5X, DDR5, CXL, coherent host memory, GDDR, and on-chip RAM as complementary design choices unless end-to-end benchmarks demonstrate that one tier alone meets the complete requirement.
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