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An atomic operation is a promise about what concurrent code may observe—not a guarantee that the CPU executes one instruction, that every thread makes progress, or that nearby memory is automatically synchronized. The language defines the promise; the compiler and any runtime support must preserve it when producing work for the target CPU.
What do atomic operations accomplish?
Atomic operations let threads safely access a shared value without exposing a torn or internally inconsistent update. Common operations include loading a value, storing one, comparing and exchanging it, and performing a read-modify-write operation such as an increment.
The atomic guarantee applies to the atomic object or location being accessed. It does not automatically make other shared data safe. In Rust and C++, conflicting unsynchronized accesses to ordinary non-atomic data can constitute a data race and lead to undefined behavior. Making a counter atomic does not, by itself, protect every field associated with that counter.
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Atomicity means concurrent operations on the atomic location obey the language’s rules for indivisible access and modification order. Memory ordering determines whether an operation also constrains the visibility and ordering of other accesses. A relaxed atomic operation can therefore be atomic without establishing a general synchronization relationship.
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How does an atomic operation get from a runtime or compiler to the CPU?
The source-language operation is a semantic request. A call such as an atomic load or compare-exchange carries an ordering, and the compiler must preserve the observations permitted by that language’s memory model. It cannot simply replace the operation with an ordinary load or store if doing so would discard the required concurrent behavior.
- Language API: The program selects an operation and ordering. In Rust, the APIs are in
std::sync::atomic; C++ exposes atomic types and operations through its standard library. The language’s rules—not the spelling of a lower-level instruction—define what the program may rely on. - Compiler representation: The compiler records the operation and its ordering in an intermediate representation. LLVM IR, for example, represents read-modify-write operations with instructions such as
atomicrmwandcmpxchg, and represents ordering operations with fences. - Optimization and lowering: Compiler passes may transform the program only while preserving those semantics. The backend then selects target instructions, adds barriers, expands an operation into a retry loop, or uses a helper routine when the target cannot directly provide the requested operation.
- Execution on the target: The CPU and platform mechanisms carry out the selected code. The result depends on the architecture, supported atomic widths, compiler, target configuration, and operation—not merely on the source-level API.
A standard library can present a stable interface while relying on compiler intrinsics and platform-specific machinery underneath. Some implementations can also fall back to a helper that uses a mutex or another mechanism. Such a fallback can preserve correctness while changing performance and progress characteristics.
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What do memory orderings mean in practice?
Memory orderings specify constraints on which observations are allowed across concurrent operations. They are not a choice between “atomic” and “not atomic”: an atomic operation remains atomic at relaxed ordering, while stronger orderings add ordering or synchronization guarantees.
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| Ordering | What it provides | What it does not provide by itself |
|---|---|---|
Relaxed |
Atomic access and a coherent modification order for that atomic location. | A general happens-before relationship for surrounding ordinary memory accesses. |
Acquire |
Constrains relevant later accesses from moving before the acquire. It can synchronize with a release when it observes the value published through the relevant atomic. | Synchronization with a release it does not observe, or protection for unrelated data without a valid synchronization structure. |
Release |
Publishes preceding accesses when a matching acquire observes the release or an applicable release sequence. | A guarantee that any acquire operation, regardless of which value it observes, synchronizes with it. |
Acquire-release |
Combines acquire and release effects, typically on a read-modify-write operation. | Automatic protection for every other shared access in the program. |
Sequentially consistent |
Provides applicable acquire/release effects and places sequentially consistent operations in a single total order. | A blanket fix for races on ordinary data or a substitute for designing correct synchronization. |
A publication example
Suppose one thread initializes ordinary data and then stores a “ready” flag with release ordering. Another thread loads that flag with acquire ordering. If the acquire observes the value published by the release (or a value covered by the relevant release-sequence rules), the release/acquire pair can establish synchronization: the initializing writes become visible to the reader under the language model.
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If the flag instead uses relaxed ordering, the flag access is still atomic, but that alone does not establish the synchronization edge needed to safely publish the ordinary data. Correctness depends on the pairing and the values actually observed, not simply on both operations being atomic.
Why can the same atomic operation use different CPU instructions?
Instruction selection is target-dependent. An architecture may have native atomic instructions, load-linked/store-conditional (LL/SC) sequences, compare-and-swap loops, fences, or platform helper routines. It may support some operand widths natively but not others. A compiler can therefore generate different code for the same source operation across targets or configurations.
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LLVM’s documented x86 lowering examples include an ordinary MOV for an atomic load, XCHG for a sequentially consistent store, LOCK CMPXCHG for compare-exchange, and XADD for atomic add or subtract. Other read-modify-write operations may require a compare-exchange loop. These are LLVM examples for x86, not universal mappings or guarantees for every compiler version, optimization context, ABI, or processor.
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How do std::sync::atomic operations work in Rust?
Rust’s atomic APIs expose operations and orderings under the language’s concurrency rules. Rust documents its atomics as currently following the C++20 atomic rules, without consume ordering. The compiler translates those operations through its intermediate representation and target backend; a particular Rust method name does not prescribe a particular CPU instruction.
Rust documents its available atomic types as lock-free, but lock-free does not mean wait-free. A read-modify-write operation may retry in a loop when another thread changes the value at the same time. Lock-free progress means the system as a whole can make progress; it does not promise that each individual thread completes within a bounded number of its own steps.
Available atomic types and widths also depend on the target. Rust documentation notes that 64-bit atomics are unavailable on some 32-bit PowerPC and MIPS targets, and that legacy ARM Linux targets may use kernel assistance. Target support changes over time, so code intended for a particular platform should check that platform’s current atomic support rather than assume every width is present.
What portability and correctness pitfalls should you check?
- Do not assume one instruction: Read-modify-write operations can involve retries, and unsupported operations may use library or platform helpers.
- Do not equate lock-free with wait-free: A lock-free operation can still retry without giving a particular thread a bounded completion time.
- Check target width support: The atomic types available on one architecture or target configuration may not be available on another.
- Keep atomic and ordinary accesses consistent: Mixing atomic and non-atomic accesses to the same concurrently accessed data can violate the language’s rules. Rust’s atomic documentation also discusses mixed-size access caveats.
- Do not use volatile as synchronization: Atomic and volatile are orthogonal. As the LLVM Atomic Instructions and Concurrency Guide puts it, “Atomic and volatile in the IR are orthogonal; ‘volatile’ is the C/C++ volatile, which ensures that every volatile load and store happens and is performed in the stated order.” Volatile does not make an access atomic or replace a synchronization protocol.
- Reason from the source-language model: LLVM ordering names help describe compiler IR, but an IR label alone is not a substitute for the rules of the language API your program uses.
How to reason about a particular atomic implementation
When evaluating an atomic operation, separate four questions rather than inferring everything from the word “atomic”:
Quick Recap
- Semantic strength: Which observations does the source language allow at the selected ordering, and is there a valid synchronization relationship for associated data?
- Compiler constraints: What ordering information reaches the compiler, and which optimizations must preserve it?
- Target strategy: Does this target use native instructions, LL/SC, a compare-and-swap loop, barriers, or a helper routine for this operation and width?
- Progress and availability: Is the operation lock-free on the relevant implementation, is it wait-free (a distinct and stronger property), and is the requested width supported on the target?
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