Free tools Windows power users keep installed
One-click scans. No signup required.
iTechGuides is reader-supported. When you buy through links on our site, we may earn an affiliate commission. As an Amazon Associate I earn from qualifying purchases. Learn more
Arm Scalable Matrix Extension (SME) is an extension to the Arm A-profile processor architecture that adds matrix-oriented instructions and architectural state. It builds on SVE and SVE2: vector outer-product instructions accumulate results in a two-dimensional storage area called ZA, while a Streaming SVE mode provides a distinct operating mode for supported operations. SME is part of a processor’s architecture and programming model—not a separate accelerator.
What SME adds to an Arm processor
SME is designed to make matrix operations a more direct part of the Arm architecture. It combines three elements: Streaming SVE mode, ZA matrix-tile storage, and instructions that form vector outer products and accumulate them into ZA. Together, these provide an architectural approach to matrix-multiplication workloads.
Arm describes SME as building on SVE and SVE2, adding capabilities to process matrices. The extension does not mean that every Arm processor supports it; the feature set depends on the processor implementation.
How Streaming SVE mode differs from ordinary SVE
SME introduces a streaming operating mode for SVE. In this mode, SME-specific operations and a subset of SVE2 instructions are available. It is not safe to assume that every SVE2 instruction usable in normal SVE operation is also available while streaming.
#1 Best Overall
The streaming vector length (SVL) can differ from the non-streaming vector length (NSVL). Arm’s 2024 introduction lists possible streaming lengths of 128, 256, 512, 1,024, or 2,048 bits; these are architectural examples, not a promise that any particular processor implements all of them. Arm’s SME introduction explains the mode and its scalable vector lengths.
What ZA is and how outer products use it
ZA is the architectural state SME adds for matrix-oriented data. It is a two-dimensional storage array that can be viewed as vectors, tiles, or tile slices. SME instructions support moving data between ZA, vector registers, and memory.
Rank #2
- Zybo Z7 comes in two APSoC variants: Zybo Z7-10 features Xilinx XC7Z010-1CLG400C. Zybo Z7-20 features the larger Xilinx XC7Z020-1CLG400C. Either variant also has the option to add the SDSoC voucher.
- A feature-rich, ready-to-use embedded software and digital circuit development board with a rich set of multimedia and connectivity peripherals to create a formidable single-board computer
- Built around the Xilinx Zynq-7000 AP SoC, with 650MHz dual-core Cortex-A9 processor and DDR3 memory controller with 8 DMA channels
- On board user interfaces include 6 push buttons, 4 slide switches, 5 LEDs, 2 RGB LEDs, and more
- Expansion opportunities with six Pmod connector ports, over 30 FPGA I/O, four Analog capable 0-1.0V differential pairs to XADC, and more
SME’s outer-product instructions take two vector inputs and accumulate—or subtract—their outer product into a ZA tile. Repeating these operations lets a program build matrix-multiplication results: input rows and columns contribute successive partial results to the output tile. This describes the programming model, not a guaranteed performance level.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
To illustrate how the storage scales, Arm’s 2024 introduction gives a 256-bit SVL example in which ZA is 32 × 32 bytes, or 1,024 bytes. That is an example configuration, not a universal ZA size. Arm’s introduction provides this example and its qualifications.
Rank #3
- There are several options for this item, this option is without header. Please click the image 2 to check the package content.
- Luckfox Lyra is a cost-effective Linux micro development board based on the Rockchip RK3506G2 to provide a simple and efficient development platform. Onboard multiple high-speed interfaces including MIPI DSl, RMll, USB, etc. to meet various application scenarios.
- The low-speed interfaces utilize Rockchip Matrix l0 design which supports multiplexing 98 function siqnals on GPlO pins, and can freely combine PWM, UART, 12C, SPl, and l2S for quick development and debugging.
- Tripe-core ARM Cortex-A7 32-bit core, with integrated VFP to support single- and double-precision floating-point operations. Built-in ARM Cortex-M0 MCU design, supports SMP and AMP configuration. Built-in 128MB DDRL3 for multi-core applications
- The low-speed interfaces adopt Rockchip Matrix IO design, which allows rich function signals to share the limited chip pins, making peripheral circuit adaptation more flexible. Built-in audio and video codec, supports multiple audio inputs and outputs, providing high-quality audio playback and recording functions
How SME relates to NEON, SVE, and SME2
| Architecture feature | Model | What distinguishes it |
|---|---|---|
| NEON | Fixed-width vector processing | Uses a fixed vector width, unlike the scalable vector-length model of SVE and SVE2. |
| SVE and SVE2 | Scalable vector processing | Provide scalable vector operations in ordinary operation; SME adds a streaming mode and ZA tile state for matrix-oriented work. |
| SME | Matrix-oriented architecture extension | Adds ZA and outer-product operations, along with Streaming SVE mode. |
| SME2 | Extension of SME | Adds multi-vector data processing, multi-vector load/store, and multi-vector predication. |
SME2 and later additions should not be confused with base SME. Arm’s 2024 overview also describes newer extensions building on SME2, including 2:4 structured sparsity and quarter-tile operations; these are later capabilities, not part of the base SME definition. See Arm’s SME2 overview and its discussion of SME2 extensions.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What SME does—and does not—say about performance or support
SME’s architectural design targets matrix processing, but the extension name alone does not establish that a processor implements it, which vector lengths it supports, or how fast a workload will run. Those answers require documentation for the specific processor and, for performance comparisons, details such as the workload, data type, compiler, and toolchain. Arm’s introductory material describes the intended architecture; it does not establish a universal speedup.
Rank #4
- The Raspberry Pi Pico is a beginner-friendly microcontroller board that uses MicroPython to give you a taste of the Internet of Things and microcontrollers. The RP2040 is a well-designed microprocessor that can be utilized in almost any Internet of Things project. It has enough power to complete the task quickly.
- 【Raspberry Pi RP2040 Microcontroller】Raspberry Pi Pico features Dual-core ARM Cortex M0+ processor, flexible clock running up to 133 MHz. With 264KB of SRAM, and 2MB of on-board Flash memory.Supports up to 16 MB of off chip flash memory via a dedicated QSPI bus
- 【Multiple Software Support】Pico has rich and complete software support, it comes with a complete Rasberry Pi official C/C++ SDK, Micropython SDK.The programming and burning of Pico need to be carried out on the computer. Supported operating systems and computers include:Raspberry Pie with Raspberry Pi OS,Other platforms equipped with Debian based Linux system Computer with MacOS, Computers with Windows, etc.
- 【Rich Hardware Interface】Raspberry Pi Pico has 30 GPIO pins, 4 pins for analog signal input and 26 × multi-function GPIO pins, 2 × SPI, 2 × I2C, 2 × UART, 3 × 12-bit ADC, 16 × controllable PWM channels.USB 1.1 supported by host and device, The installation mode can be flexibly selected by users to facilitate welding with other development boards.
- 【Build Project in Tiny Size】Only 2.1cm*5.1cm ( as small as your thumb). Pico has been designed to use either soldered 0.1" pin-headers or can be used as a surface-mountable 'module'.
Likewise, example vector widths and storage sizes explain how SME can be configured; they are not specifications for every implementation. Check a processor’s own official documentation before relying on SME or a particular SVL in software.
PC Slower Than It Used to Be?
A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11Crashes, No Sound, or Screen Glitches?
Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteQuick Recap
In brief
- SME is an Arm A-profile architecture extension built on SVE and SVE2, not a separate matrix chip.
- Its defining addition is ZA, two-dimensional architectural storage for matrix tiles.
- Outer-product instructions accumulate vector-derived results into ZA, supporting matrix-multiplication workflows.
- Streaming SVE is distinct from ordinary SVE and supports only a subset of SVE2 instructions.
- SME2 adds capabilities beyond base SME, so its additions should be identified separately.
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
