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AI computing is being reshaped not by transistor scaling alone, but by how effectively a system moves data between processors and memory, delivers power, removes heat, and connects multiple dies. “Beyond Moore’s Law” means adding new ways to improve complete systems while transistor scaling continues—not declaring scaling over.
Why AI is changing the semiconductor problem
AI workloads place heavy demands on both computation and data movement. A processor can only work on data that reaches it; moving that data consumes bandwidth, time, and energy. As systems grow, power delivery and heat removal become design constraints alongside transistor density and processing speed.
The Semiconductor Industry Association’s 2025 overview describes progress as a full-stack effort: scaling continues, while software, materials, chip design, architectures, and packaging offer additional routes to meet application needs such as high bandwidth, low power, lower latency, and thermal stability. Those are goals and areas of innovation, not guarantees that every new technique will improve every workload.
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Moore’s Law is commonly used to describe the historical trend of increasing transistor counts on integrated circuits over time. It is not a promise that every chip generation will deliver the same cost, performance, or power improvement, and a process-node label should not be read as a literal measurement of a transistor feature.
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Intel Newsroom’s 2025 explainer answers “Definitely not” to the question of whether Moore’s Law is dead. That is Intel’s perspective, but it makes a useful distinction: continued scaling can coexist with other innovation paths. The practical change is that transistor counts alone are less helpful for judging a system. Memory bandwidth, interconnects, packaging, power, heat, yield, and total cost also matter.
Device and power innovations: changing the transistor and its connections
Gate-all-around and nanosheet transistors
In a gate-all-around design, the transistor gate surrounds the channel, giving the gate control from more sides than in a conventional fin-based structure. Nanosheet implementations use thin channel sheets. The aim is stronger electrostatic control as devices shrink, which can support improvements in performance, power, or density. The result depends on the implementation and process; the structure alone does not establish a particular system-level gain.
Intel describes its RibbonFET technology as a gate-all-around approach, while TSMC describes its own nanosheet transistor development. These are company descriptions of their technologies and roadmaps, not independent head-to-head measurements.
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Backside power delivery
Conventional chips route power and signals through the front side of the wafer. Backside power delivery moves power connections to the other side of the transistor layer, reducing competition between power wiring and signal routing. In principle, that can help with routing congestion and power behavior; actual outcomes depend on manufacturing and the design.
Intel calls its implementation PowerVia. In an announcement on April 24, 2024, TSMC described a backside power rail in its A16 plan. That announcement is evidence of a planned approach at that time, not confirmation of its 2026 production status. Neither company’s stated benefits should be treated as neutral benchmark results.
Chiplets, HBM, and packaging: building a system from multiple dies
A chiplet is a smaller die designed to be integrated with other dies in a package. Rather than placing every function on one large die, a designer can combine compute, memory-related functions, or other components. Different dies may use different process generations or come from different sources, where the design and supply arrangements allow.
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Intel says smaller chiplets can be easier to yield than a single large die approaching reticle limits. That is Intel’s description of a potential manufacturing advantage, not a guarantee: integration adds package cost, design work, testing needs, and interconnect requirements. The relevant question is whether the complete design benefits after those trade-offs.
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| Approach | How it connects dies | What it is intended to address |
|---|---|---|
| 2.5D integration | Multiple dies sit side by side and connect through an interposer or bridge. | High-bandwidth connections between nearby dies, including compute and memory. |
| 3D stacking | Dies are stacked vertically, with connections between layers. | Short, dense connections where vertical integration suits the design. |
| Chiplet integration | Two or more dies are combined in a package; the package may use 2.5D or 3D connections. | Modularity and combining functions or process technologies. |
These terms describe related but distinct design choices: “chiplet” refers to the use of multiple dies, while 2.5D and 3D describe ways to arrange and connect them. Intel describes packaging options including EMIB 3.5D and Foveros Direct 3D. IBM Research describes bringing multiple technologies together at package level and reports hybrid-bonding research. Those descriptions do not provide a neutral comparison of the approaches.
HBM and the distance to memory
High-bandwidth memory (HBM) places memory stacks close to compute in a package, providing a wide connection for moving data. This can help workloads that need substantial memory bandwidth, but it does not remove limits on memory capacity, power, package complexity, supply, or the rest of the system.
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TSMC’s April 24, 2024 announcement describes CoWoS as placing processor cores and HBM stacks on an interposer. It describes SoIC separately as a 3D-stacking solution. CoWoS and SoIC should not be used as interchangeable names for one packaging method: one description emphasizes integration on an interposer, the other vertical stacking.
Packaging is also a manufacturing capability
Advanced packaging has its own manufacturing and yield challenges; connecting dies is not merely a final assembly step. IBM Research says its Bromont facility manufactures 100,000 advanced flip-chip modules each week. That is IBM’s reported output for that facility, not an industry-wide production statistic or a measure of AI-chip output.
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Photonics, materials, and quantum-related work: what remains emerging
Silicon photonics and co-packaged optics
Optical links carry data using light rather than only electrical signals. Silicon photonics and co-packaged optics aim to bring optical communication closer to computing components, potentially addressing data movement at high bandwidth or over longer distances. Their value depends on factors such as energy per bit, reach, packaging, reliability, and manufacturing readiness.
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TSMC and IBM identify photonics or co-packaged optics as development directions. TSMC’s April 2024 announcement included target dates for related plans; those historical targets do not establish what is broadly available in 2026. The cited descriptions also do not establish broad production maturity for these approaches.
New materials and AI-assisted co-design
The U.S. Department of Energy frames microelectronics challenges around miniaturization, processing speed, power consumption, thermal management, and operating environment. Its proposed AI-driven, full-stack co-design ecosystem is intended to accelerate materials and manufacturing research and development. DOE also identifies advanced materials and nanofabrication as research capabilities. These efforts broaden the options researchers can investigate; they are not evidence that a new material is ready to replace mainstream commercial chips.
Quantum-related microelectronics
DOE also includes quantum-related technologies, such as cryogenics, in its microelectronics research capabilities. Such work can depend on specialized operating conditions and targets applications beyond ordinary CPU or GPU acceleration. It should be understood as a research frontier, not a drop-in AI processor option.
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How to judge which path fits an AI system
There is no universally best architecture in the cited material, and the sources do not provide a neutral, current cross-vendor comparison of performance per watt, cost, yield, or deployment maturity. Evaluate a design against the workload and the complete system rather than treating a node label or packaging method as a verdict.
- Workload: Establish whether the application is constrained by compute, memory bandwidth, capacity, latency, or data movement between devices.
- Power and heat: Account for power delivery, cooling, and thermal behavior under sustained operation, not just peak specifications.
- Interconnect: Consider bandwidth and latency between compute and memory, between chiplets, and between systems.
- Manufacturing: Ask how the design affects die and package yield, testing, supply availability, and production readiness.
- Total cost: Include packaging and integration complexity as well as the cost of the dies; the sources do not establish a comparable cost figure across these approaches.
- Evidence and maturity: Separate technologies described as manufacturing capabilities from announced roadmaps, ongoing development, and research proposals. A vendor target date or stated benefit is not an independent result.
The strongest conclusion is not that one technology replaces scaling. AI-era semiconductor progress is a portfolio: better devices, power delivery, memory proximity, interconnects, packaging, and research into new materials or computing approaches. Their value emerges only when the whole system meets a workload’s performance, power, thermal, manufacturing, and cost requirements.
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