At 65 nm, Qualcomm’s MSM6260 and Texas Instruments’ Nokia-packaged processor 4377401 illustrate two different ways process scaling could shape a mobile-chip design in 2007. The useful comparison is not which chip was faster or smaller: they served different functions, and the reported figures come from vendor claims and separate analysis rather than a common benchmark.
What the two 65 nm examples were
Qualcomm MSM6260: a 3G baseband modem
John Boyd’s May 14, 2007 account describes the MSM6260 as a TSMC 65 nm baseband modem intended for mainstream 3G handsets. It supported W-CDMA/UMTS and GSM/GPRS/EDGE, and Qualcomm used a common platform intended to serve multiple handset designs. The article reports that the MSM6260 was RF- and pin-compatible with Qualcomm’s MSM6245 and MSM6255A.
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The preceding MSM6250A used TSMC 90 nm CMOS. This makes it the more relevant reference point for the reported Qualcomm process transition, though it does not turn the two chips into a controlled performance comparison. EE Times’ 2007 article supplies the historical device description.
TI 4377401: a processor in a Nokia package
The second example is processor 4377401, identified in the article as a TI 65 nm low-power CMOS device in a Nokia package. The account describes its process and packaging context, but it does not establish that this processor performed the same job as Qualcomm’s baseband modem. As a result, the examples are useful for discussing design partitioning and process choices, not for ranking the chips on a shared workload.
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What scaling from 90 nm meant in the Qualcomm example
Boyd reported TSMC’s claims that its 65 nm process offered nearly double the density, 50% greater speed, and 20% lower standby power than its 90 nm process. Those are TSMC process claims as reported in 2007, not results from a head-to-head MSM6260-versus-MSM6250A benchmark.
The account also describes TSMC process techniques including strain associated with shallow-trench isolation, silicide, and cap layers, along with nickel silicide for ultrashallow junction formation. These are details of the historical process description, not specifications for today’s 65 nm offerings.
What the reported chip analysis found
Area and SRAM
Semiconductor Insights’ analysis, as reported by Boyd, found an almost 60% reduction in SRAM cell size for the MSM6260 relative to the earlier generation. Yet the article says the overall die size remained similar to the MSM6250A’s, which Boyd interpreted as evidence of substantially greater functionality in the newer device. The combination matters: smaller memory cells do not necessarily mean a smaller complete chip when other circuitry or capabilities change.
The article also notes a gate thickness of roughly 2 nm in both generations. That observation belongs to the specific chips examined in 2007; it should not be treated as a universal or current specification for a process node.
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Interconnect stack
Boyd describes the MSM6260 as using six copper interconnect levels topped by an aluminum layer. The TI 4377401 account likewise identifies six copper levels and a top aluminum layer, with OSG low-k intermetal dielectrics. Shared interconnect counts do not establish that the devices had identical layouts, electrical behavior, or performance.
How to read TI’s process figures
For TI’s 65 nm low-power CMOS, the 2007 article reports that the process could halve 90 nm design area, raise transistor performance by 40%, and reduce idle-transistor leakage by a factor of 1,000. These are TI process-technology claims as reported by Boyd; the article does not provide an independent test protocol or show that the figures were measured on processor 4377401 itself.
The numbers also describe different quantities: design area, transistor performance, and idle-transistor leakage. They should not be combined into a single score or directly compared with TSMC’s claims without matching definitions, conditions, and test methods.
Integration versus decoupling
Boyd’s central design interpretation is that Qualcomm favored greater integration and a reduced form factor, an approach that can make a platform compact but leaves less flexibility to optimize process and design independently. TI’s approach is described as more decoupled: separating process and design interactions can allow independent optimization, while potentially requiring more separate devices in a multichip package.
Do these 3 things before closing this tab:
1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsThese are strategies, not a universal verdict. The practical trade-off depends on what a handset platform needs: integration can reduce package complexity and form factor, while partitioning can preserve design flexibility. The article does not quantify either strategy’s cost, power, or performance advantage in a controlled test.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What this comparison can—and cannot—show
| Dimension | Qualcomm MSM6260 example | TI 4377401 example |
|---|---|---|
| Device context | TSMC 65 nm baseband modem for mainstream 3G applications, supporting W-CDMA/UMTS and GSM/GPRS/EDGE. (Boyd, 2007) | Processor in a Nokia package using TI 65 nm low-power CMOS. (Boyd, 2007) |
| Prior-generation or scaling reference | MSM6250A identified as a TSMC 90 nm CMOS predecessor. (Boyd, 2007) | TI process claims compare 65 nm with 90 nm; a specific predecessor chip is not stated in Boyd’s account. |
| Area and memory | Overall die size reported as similar to MSM6250A; Semiconductor Insights’ analysis reported almost 60% smaller SRAM cell size. (Boyd, 2007) | TI process technology was reported to halve 90 nm design area; this is a process claim, not a measured comparison of the complete 4377401 package. (Boyd, 2007) |
| Performance and power figures | TSMC claimed 50% greater speed and 20% lower standby power at 65 nm than at 90 nm. (Boyd, 2007) | TI process technology was reported to improve transistor performance by 40% and reduce idle-transistor leakage by a factor of 1,000 versus 90 nm. (Boyd, 2007) |
| Interconnect | Six copper levels and a top aluminum layer. (Boyd, 2007) | Six copper levels, a top aluminum layer, and OSG low-k intermetal dielectrics. (Boyd, 2007) |
| Design interpretation | Greater integration and reduced form factor, with less flexibility to optimize process and design separately. (Boyd, 2007) | More decoupled process/design interaction for flexibility, potentially with more separate devices in a multichip package. (Boyd, 2007) |
The entries are not directly comparable performance measurements: the products differ in function, and the reported statistics have different owners and measurement contexts. The EDN republication reproduces the same May 14, 2007 article; it corroborates the accessible account, not the underlying process claims independently.
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