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What scan design does
A sequential circuit stores state in elements such as flip-flops. In ordinary operation, those elements respond to the circuit’s logic and inputs. In scan mode, scan-capable storage elements can instead be connected as one or more serial chains. Test data is shifted into a chain to set internal state; after the circuit is stimulated, its state is shifted out for observation.
This improves two important properties for testing: controllability, or the ability to set internal nodes to useful values, and observability, or the ability to see the effects of those values. ATPG tools can use that access to create test patterns for a more tractable problem than testing the same internal logic only through the chip’s normal inputs and outputs.
Scan is a design-for-testability (DFT) method, not a guarantee that every fault will be detected. Coverage still depends on the design, the fault models being targeted, test constraints, and the quality of the generated patterns. Adding scan also has costs: scan cells and their connections use hardware resources, and shifting data through chains takes time and consumes power.
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How scan design evolved
Internal state becomes accessible
IEEE’s Technology Navigator overview describes scan-based methods as having become systematic engineering practice in the 1970s. That supports a broad account of the period, not a precise invention date or a claim about a single inventor. The available historical account does not establish a detailed sequence of early events.
The central idea is to make a chip’s sequential state accessible in test mode. With internal state easier to set and inspect, engineers can test logic that would otherwise be difficult to exercise or observe from chip pins alone.
Boundary scan extends access to chip pins and boards
Boundary scan applies related test access at a chip’s I/O boundary, helping engineers test board interconnects as well as chip interfaces. It is commonly associated with JTAG and standardized as IEEE 1149.1. This adds a route for testing connections across a board; it is related to internal scan but serves a distinct access purpose.
IJTAG makes embedded instruments accessible
IEEE 1687, known as IJTAG, supports reconfigurable access networks for embedded instruments inside a design. Rather than treating every instrument as an isolated endpoint, a network can configure routes to reach the instrument needed for a particular operation. That flexibility introduces scheduling questions: access and reconfiguration contribute to total test time, and a schedule must respect power-domain constraints.
Chiplet test spans multiple dies
As products integrate multiple dies in one package, testing must account for access to DFT functions across chiplets, including after assembly. IEEE 1838-2019 defines mandatory and optional structures for accessing those functions in multi-die systems. The standard addresses the test-access architecture; it does not, by itself, eliminate the need to secure that access.
Design constraints that shape scan architectures
Coverage and fault models
Scan access can make internal logic easier for ATPG to control and observe, but a design’s test plan still needs to specify what kinds of faults it targets and how patterns will detect them. An architecture that is suitable for one chip and test flow is not automatically the best choice for another.
Shift power and thermal limits
Shifting scan data across a large design can create substantial switching activity, which raises power consumption and thermal concerns. A 2024 IEEE paper, “Improved Scan Chain Stitching for Reducing Test Power,” discusses scan-cell modifications, shift-power optimization, and partitioning scan chains as ways to address the problem. The available abstract does not establish a universal improvement percentage, so no single reduction figure can be attributed to these approaches here.
Test time and access scheduling
Test time depends not only on how many patterns a design needs but also on the time to shift and capture them, and, in reconfigurable networks, to set up access paths. A study abstract on power-aware scheduling for IEEE 1687 multi-power-domain networks describes optimization-based scheduling approaches. Its available summary does not support a comparative claim that one approach is faster than another across designs.
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Security of test access
Access that helps legitimate testing can also expose internal state or provide a path to alter it if left available to an unauthorized party. The issue becomes especially significant when access crosses chiplet boundaries. In a 2024 IEEE European Test Symposium paper, researchers propose combining scan encryption with message-integrity verification for IEEE 1838-compliant access networks. The goal is to protect confidentiality and verify that test messages have not been altered.
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In that paper’s evaluation, the authors report less than 1% area overhead for designs exceeding five million gates and less than 1% test-time overhead for typical DFT implementations. These figures describe the paper’s proposed protection approach and evaluation context; they are not general overhead figures for scan design or for IEEE 1838 systems as a whole.
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Test structures must fit the full silicon lifecycle
DFT is increasingly discussed as a lifecycle concern rather than only a production-line activity. A 2024 IEEE Design & Test review, “The Future of Design for Test and Silicon Lifecycle Management,” examines in-system and in-field operations, including contexts such as automotive electronics and data centers. It points to a direction for the field, not evidence that every product performs field scan or exposes the same diagnostic capabilities after deployment.
Lifecycle use changes the design question: engineers must consider not only how to test a new chip during manufacturing, but also which checks or diagnostic operations are useful later, when they can safely run, and who is authorized to invoke them. Those decisions connect test access to reliability requirements and security policy.
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Power-aware, scheduled access will matter more
More instruments, power domains, and dies can make access networks more capable but harder to operate efficiently. Future scan and IJTAG planning must balance coverage and access time with shift and capture power, thermal limits, reconfiguration overhead, and the ability to test only the parts of a system that are safe to exercise at a given moment.
Architecture choices remain design-specific
There is no universally best scan architecture. When comparing options, teams need to weigh the fault coverage they require against hardware area and design complexity, test time, shift and capture power, power-domain behavior, access security, and support for in-system diagnosis. The right balance depends on the chip, its test flow, and its packaging and lifecycle requirements.
What the history says about the future
The broad progression is from access to internal sequential state, to standardized boundary access across boards, to reconfigurable access for embedded instruments, and then to test structures that cross chiplet boundaries and support lifecycle operations. The standards and later work establish these capabilities, but they do not prove when each transition became dominant. The continuing challenge is to make test access useful without allowing its hardware cost, power demand, time overhead, or security exposure to outweigh its value.
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