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Infineon Technologies AG and Swiss quantum startup ZuriQ AG expanded their collaboration on October 7, 2026, to develop trapped-ion quantum-computing hardware that can scale beyond a previously reported 3×3 array of nine individually controlled ions. The companies describe larger arrays as a future goal; they have not announced a target qubit count, timetable, performance results, or commercial product.
What did ZuriQ and Infineon announce?
The companies announced an expanded development collaboration in Munich and Zurich on October 7, 2026. It builds on earlier joint work and aims to advance scalable quantum chips by combining ZuriQ’s trapped-ion architecture with Infineon’s semiconductor manufacturing and integration capabilities. Infineon’s announcement describes a development effort, not a finished quantum computer or a commercial launch.
What has the partnership demonstrated so far?
Infineon and ZuriQ report that their earlier work produced a two-dimensional 3×3 array of nine individually controlled ions. Infineon calls it the largest two-dimensional array of its kind to date. That distinction is the companies’ characterization; the announcement does not provide an independent validation or detailed experimental dataset. The nine-ion array is a reported prior result, while significantly larger qubit counts remain a future objective.
The announcement does not specify how many qubits the next system should contain, when it might be ready, or how it performs on measures such as fidelity or operating speed.
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How is ZuriQ’s Penning micro-trap intended to scale?
ZuriQ’s approach confines ions in a two-dimensional Penning micro-trap. The companies say electric and magnetic fields move ions directly across the chip. They contrast this layout with conventional trapped-ion systems based on one-dimensional ion chains, which can require junction structures to route ions between parts of a device. Their scaling thesis is that a two-dimensional arrangement without complex junctions could make larger arrays easier to accommodate; the reported nine-ion array does not, by itself, establish that larger-scale operation has been achieved.
ZuriQ’s earlier explanation of the partnership adds a fabrication rationale: the company says its Penning approach avoids high-voltage and high-frequency electric signals that dissipate power into the substrate, and presents silicon chip carriers and standardized industrial CMOS processes as a path toward integration. These are ZuriQ’s stated design aims, not a report that the chip is already manufactured at commercial scale. ZuriQ’s July 2025 partnership announcement describes that rationale.
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What does each company contribute?
- ZuriQ: Its Penning micro-trap architecture and quantum-chip design expertise.
- Infineon: Semiconductor process development and manufacturing experience, advanced packaging, and integrated photonics capabilities.
The intended bridge is from a laboratory-stage trapped-ion demonstration toward hardware that can be manufactured and integrated at greater scale. Infineon describes a quantum processing unit (QPU) as the core chip that runs quantum calculations and says it works across trapped-ion, superconducting, and silicon-spin technologies. Infineon’s quantum-chip overview provides that broader company context.
How does this fit Infineon’s other quantum work?
Infineon also described participating in European quantum pilot lines in an April 2026 announcement, including CHAMP-ION, an initiative to establish an ion-trap quantum-chip manufacturing line. That activity spans multiple quantum technologies and is separate from the ZuriQ partnership in the available announcements; no source connects CHAMP-ION directly to this collaboration. Infineon’s pilot-line announcement outlines that wider industrialization work.
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What milestones remain unspecified?
The October 2026 announcement sets a direction—significantly larger qubit counts—but leaves the practical milestones open. It gives no numerical array target, delivery date, benchmark, manufacturing volume, price, or plan for commercial availability. Until those details and results are published, the partnership is best understood as hardware development aimed at scalability, rather than a product launch or proof of a commercially scalable system.
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