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At the 2026 OCP Global Summit, Intel, AMD and Nvidia announced six pieces of an emerging AI-factory stack: an air-cooled inference accelerator, ultra-dense CPU racks, configurable CPU/GPU systems, a new host CPU, open cluster-management software and a standardized liquid-cooled rack design. Several announcements describe sampling, reference architectures or future production rather than products available immediately.
Why OCP 2026 mattered for AI infrastructure
The announcements covered nearly every layer between an AI workload and the building that runs it. Intel focused on inference silicon and CPU density; AMD presented an open rack blueprint and a future EPYC processor; Nvidia addressed both the software control plane and the physical rack standard needed for very high-power systems.
CRN, citing 650 Group, reported attendance of about 15,000 people. That figure is a reported event estimate, not a vendor shipment metric. The more important signal was the breadth of the announcements: performance figures were paired with cooling, power-delivery, interoperability and deployment-timing details.
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1. Intel GPU D-Series (Crescent Island) targets air-cooled inference
Intel disclosed the GPU D-Series, code-named Crescent Island, as a PCIe inference accelerator designed for large language models, long-context inference and multiple concurrent services. Intel said customer sampling is already in progress.
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| Specification | Announced maximum | Qualification |
|---|---|---|
| FP8 performance | Up to 1.3 PFLOPS | Vendor-stated peak figure |
| Memory bandwidth | 1.5 TB/s | Vendor-stated specification |
| Local memory | Up to 480 GB LPDDR5X | Maximum stated capacity |
| Board power | 350 W TDP | Designed for air-cooled PCIe deployment |
The combination is aimed at serving models that need substantial memory capacity and bandwidth without moving to a liquid-cooled accelerator tray. A PCIe card can fit into existing server designs more readily than a purpose-built rack module, although actual server compatibility, software support and delivered performance will depend on Intel’s production implementation and customer systems. Sampling means selected customers are evaluating hardware; it does not establish broad commercial availability.
2. Intel showed Xeon 6+ racks with more than 46,000 cores
Intel demonstrated Open Rack v3-oriented designs exceeding 46,000 Xeon 6+ cores in one rack. A cited configuration used a 133.45 kW rack envelope. Those figures describe a high-density system design, not the power draw or core count of every Xeon 6+ installation.
In the demonstration, the CPUs handle orchestration, data processing and I/O while keeping accelerators supplied with work. Intel also highlighted Clearwater Forest parts with as many as 288 efficiency cores in a 450 W package. A package-level number should not be confused with the total rack specification: the rack figure includes many processors and the surrounding power and infrastructure.
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This approach matters for AI factories that need large numbers of host threads for preprocessing, scheduling, storage traffic and service coordination. It can also increase facility-design pressure because a 133.45 kW rack envelope requires carefully engineered power delivery and cooling.
3. AMD Helion is an open, configurable rack blueprint
AMD introduced Helion as a customizable rack design rather than a single fixed server. It can combine EPYC CPUs and Instinct GPUs, or operate as a CPU-only rack, and it supports either air cooling or direct liquid cooling.
| Helion option | What AMD describes |
|---|---|
| Mixed compute | EPYC CPUs paired with Instinct GPUs |
| CPU-only | Up to 32,768 Zen 6 cores per rack |
| Cooling | Air or direct liquid cooling |
| Interoperability target | OCP ORv4 and DC-MHS compliance, as reported for the revised design |
| Availability timing | OEM configurations planned from November 2026 |
Helion’s value is choice: a system builder can tune the rack for accelerator-heavy training and inference, CPU-heavy services or a mixture of both. The 32,768-core figure applies to the CPU-only configuration and should not be read as the capacity of every Helion rack. OEM availability planned for November 2026 also means buyers will need to obtain a system from a participating manufacturer; AMD’s blueprint itself is not a ready-to-order server.
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4. EPYC Verano brings a 192-core host-CPU design
AMD chief executive Lisa Su announced EPYC Verano, described as a 6th-Generation EPYC Venice processor. AMD said it will scale to 192 cores and add an LPDDR memory interface. The design prioritizes low system power and higher bandwidth between the CPU and GPUs.
Production is planned for the first half of 2027, so the announcement is a forward-looking platform disclosure rather than a current purchasing option. An LPDDR interface can reduce memory-system power and support compact designs, while better CPU-to-GPU bandwidth can help host processors feed accelerators more efficiently. Actual memory capacity, supported systems and performance comparisons were not stated in the announcement.
5. Nvidia open-sourced DSX cluster-management components
Nvidia said Run:ai and related DSX components are available under open-source licenses. The release covers operational software that controls how GPU resources are scheduled, divided and monitored across clusters.
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- KAI Scheduler
- GPU Fractioning Operator
- KAI Resource Management
- Workload Map
- Config Manager
- Cluster Readiness Engine
- Rack Management Service
- Cluster API Provider for NVIDIA Infrastructure Controller
Together, these components address the control plane rather than the compute silicon itself. Scheduling and fractioning can help organizations assign portions of GPUs to different workloads; readiness, configuration and rack-management services target the operational work required to run larger installations. “Open source” does not automatically mean every feature has identical support, licensing terms or integration effort, so teams will still need to review each component’s license and maturity before standardizing on it.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.6. Nvidia contributed Vera Rubin MGX 1.2 designs to OCP
Nvidia contributed its third-generation MGX rack and compute-tray designs to the Open Compute Project. The Vera Rubin-era MGX 1.2 architecture is intended for very high-density systems and supports racks up to 250 kW, according to Nvidia.
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- Interoperable rack interconnects for connecting systems built by different manufacturers around the design.
- A liquid-cooled 5,000-amp busbar for distributing exceptionally high current.
- Configurable I/O bays so rack builders can adapt connectivity layouts.
- Fanless, liquid-cooled compute trays.
Contributing the design to OCP is intended to turn a vendor-developed AI-factory architecture into a specification that other companies can manufacture and extend. The 250 kW figure is a supported rack architecture limit, not a statement that every Vera Rubin deployment will consume that much power. At this scale, facility plumbing, electrical distribution and service procedures are as consequential as accelerator specifications.
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How the six announcements fit together
| Announcement | Primary workload role | Scale or headline figure | Deployment status | Thermal/interoperability angle |
|---|---|---|---|---|
| Intel GPU D-Series | Inference acceleration | 1.3 PFLOPS FP8, 480 GB LPDDR5X, 350 W | Customer sampling in progress | Air-cooled PCIe card |
| Intel Xeon 6+ rack | Orchestration, data and I/O | More than 46,000 cores; 133.45 kW envelope | Demonstrated rack design | Open Rack v3-oriented |
| AMD Helion | Configurable CPU/GPU or CPU-only rack | Up to 32,768 Zen 6 cores in CPU-only form | OEM configurations planned November 2026 | Air or direct liquid cooling; ORv4/DC-MHS alignment |
| AMD EPYC Verano | Host CPU for AI systems | Up to 192 cores | Production planned for first half of 2027 | LPDDR interface; improved CPU-to-GPU bandwidth focus |
| Nvidia DSX software | Cluster scheduling and management | Eight named open-source components | Open-source availability announced | Software control plane |
| Nvidia Vera Rubin MGX 1.2 | Rack, tray, power and cooling infrastructure | Supports racks up to 250 kW; 5,000 A busbar | Contributed to OCP as a design | Liquid cooling and interoperable rack architecture |
What buyers and infrastructure teams should take away
These announcements are complementary rather than six competing products. Intel’s D-Series addresses inference in a conventional PCIe form factor, while Intel’s Xeon design supplies dense host capacity. AMD’s Helion provides a configurable system-level template, and Verano points to a lower-power, high-core-count host processor for 2027 systems. Nvidia’s DSX software targets cluster operations, while MGX 1.2 addresses the physical rack needed when power and heat move far beyond ordinary server limits.
Readiness varies sharply. The D-Series is sampling; Helion OEM systems are planned for November 2026; Verano production is planned for the first half of 2027; and MGX is being contributed as an OCP design rather than sold as a single standardized appliance. Organizations planning purchases should therefore separate demonstrated capability from orderable hardware, and evaluate software, power, cooling and serviceability alongside compute figures.
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