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3D-stacked memory places multiple memory dies on top of one another and connects them with dense vertical electrical paths. High Bandwidth Memory (HBM) is a prominent example: its DRAM dies form a vertical stack, while the HBM stack can sit beside a CPU or GPU on a silicon interposer inside the same package. The processor is not necessarily stacked directly above the memory.
What “3D stacked” means
The term describes how complete memory dies are arranged and connected in a package: several dies are placed vertically, one above another, instead of being laid out only side by side. It is a packaging and interconnect approach, not a claim that the memory cells inside an individual DRAM die are themselves arranged as a stack.
In HBM, through-silicon vias (TSVs) provide vertical electrical paths through silicon dies, and microbumps connect dies in the stack. Micron describes HBM as a specialized, high-performance 3D-stacked SDRAM architecture and explains that multiple DRAM dies may be stacked above a base die. Micron’s HBM overview and FAQ provides its manufacturer explanation.
How the memory stack connects to a processor
There are two distinct physical arrangements to keep in mind. First, the DRAM dies are stacked vertically within the HBM unit. Second, that HBM stack and a CPU or GPU can be positioned alongside one another on a silicon interposer within a system-in-package. The interposer provides connections between them; it does not mean the processor sits directly on top of the memory stack.
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This differs from a conventional flat arrangement, where chips communicate through package or board-level routes. Short, dense connections in an advanced package help support HBM’s high-bandwidth design, but the TSVs alone do not determine performance. The interface, memory controller, product generation, and system integration also matter.
Why HBM can provide high bandwidth
HBM combines vertical stacking with a wide, parallel interface and multiple channels. Micron describes one HBM cube as having a 1024-bit interface and 32 independent channels. A wider interface can move more data in parallel than a narrower connection, although actual system performance depends on the specific memory and processor implementation.
For context, Micron’s current HBM4 product page states a 2048-pin bus, speeds greater than 11.0 Gbps, and bandwidth greater than 2.8 TB/s per stack. Those are Micron’s HBM4 specifications, not a result from an independent head-to-head test. Micron’s HBM4 page gives the stated product details.
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Stack height and specifications vary by product
“3D stacked” does not specify one fixed height, capacity, bandwidth, or thermal profile. These depend on the generation and product. Samsung says HBM products commonly use 4-high, 8-high, or 12-high configurations, depending on generation. Its HBM page associates HBM3E with up to 9.2 Gb/s per pin and 1,180 GB/s per stack. These are Samsung-published product specifications, not independent comparative measurements. Samsung’s HBM product page lists the figures.
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Samsung’s 2019 announcement of 12-layer 3D-TSV technology cited more than 60,000 TSV holes and a package thickness of 720 micrometres, which it said matched its then-current eight-layer HBM2 products. Those values describe that particular 2019 announcement and should not be treated as specifications for all HBM stacks today. Samsung’s 2019 announcement describes that package.
| Example | Vendor-stated figure | Scope |
|---|---|---|
| HBM cube interface | 1024-bit interface; 32 independent channels | Micron’s description of one HBM cube |
| HBM4 | 2048-pin bus; greater than 11.0 Gbps; greater than 2.8 TB/s per stack | Micron’s HBM4 product specifications |
| HBM3E | Up to 9.2 Gb/s per pin; 1,180 GB/s per stack | Samsung’s HBM product specifications |
| 12-layer 3D-TSV package | More than 60,000 TSV holes; 720 micrometres thick | Samsung’s 2019 announcement; thickness compared with its then-current eight-layer HBM2 products |
The figures above come from different vendor pages, generations, and product contexts. They are not a controlled comparison, and the two bandwidth values should not be read as a benchmark ranking.
How 3D-stacked memory differs from conventional DDR
Both HBM and DDR are forms of DRAM, but their packaging and interface organization differ. HBM uses stacked dies, dense vertical connections, and a wide parallel interface, and is integrated close to a processor in a package. Conventional DDR memory is typically supplied as a module connected to a system through its memory interface. The HBM architecture is designed for high bandwidth in specialized systems; it is not simply a taller or faster drop-in replacement for a DDR module.
Where you encounter it
HBM is used in specialized processor systems where high memory bandwidth is important, including systems built around CPUs or GPUs. Because it is integrated into the processor package rather than installed as an ordinary user-replaceable memory module, it is generally a system-design choice, not a consumer upgrade. Whether a particular system uses HBM depends on its processor and package design.
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