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High Bandwidth Memory (HBM) is made by fabricating DRAM dies, forming through-silicon vias (TSVs) to carry signals between them, thinning and preparing the wafers, and bonding the dies into a vertical stack for packaging. Lithography defines where key features such as TSVs and package wiring will be made; etching, deposition, plating, and polishing turn those patterns into physical structures.
What HBM manufacturing has to accomplish
HBM combines multiple DRAM dies in a vertical stack. TSVs—conductive paths through silicon—connect the stacked dies so signals can travel between them. Prepared bumps provide connection points for bonding, while a base die or wafer and the eventual package provide further connections to the system.
The sequence below follows the via-middle example described by SK hynix in its October 5, 2023 back-end process explainer. In that example, transistors are formed before the TSVs, and TSV construction takes place before back-end-of-line (BEOL) wiring is complete. It is one documented flow, not a universal recipe: suppliers and product generations can differ in their integration and packaging choices.
How the manufacturing sequence works
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Build the DRAM circuitry
Front-end wafer processing forms the memory circuitry. In the SK hynix via-middle example, CMOS transistors are made before TSV construction begins.
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Pattern and etch the TSV locations
Lithography transfers the designed via locations into a hard-mask pattern. That mask guides deep etching into the silicon, creating openings for the TSVs.
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Insulate and fill the vias
An insulating film, such as oxide, isolates the future copper conductor from the surrounding silicon. A metal barrier layer is added, then copper is electroplated into the openings. Chemical-mechanical polishing (CMP) removes excess copper from the surface.
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Complete wafer wiring and form bumps
The wafer proceeds through BEOL processing to complete its wiring. Bumps are formed for connections between dies or between a die and an interposer. In packaging, lithography can also pattern redistribution wiring and openings for package connections.
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Support the wafer, then thin it
A temporary adhesive bonds the bumped frontside to a carrier. The carrier supports the wafer during backgrinding, which reduces its thickness and helps manage warpage while the backside is processed. Backside bumps are then formed, and the temporary carrier is debonded.
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Dice and bond the dies into a stack
The prepared core dies are diced and stacked onto a base die or base wafer using their bump connections. Depending on the process, bonding may use mass reflow or thermocompression. The exact choice is supplier- and product-specific.
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Mold, finish, test, and ship
The stack is molded and ground to the required package thickness, then diced into stacked units. SK hynix describes HBM as an example of known-good stacked die prepared for later 2.5D package integration. This package-level sequence follows the company’s published explainer; it does not disclose every supplier’s process details.
What lithography does—and what it does not do
Lithography transfers a designed pattern into photoresist or a hard-mask layer. For TSV formation, that pattern determines where the silicon will be etched. In package processing, patterned resist can guide electroplating of wiring or define openings for other package features. Pattern placement and fidelity therefore constrain where vias and connections can be made.
Lithography does not, by itself, make an electrical connection. It defines where later operations act: etching opens the silicon or other material; deposition adds insulating and barrier films; plating fills conductive features; and CMP removes unwanted surface material and planarizes the wafer. The electrical path is the result of that integrated sequence.
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Why stacking and thinning matter
Vertical stacking places multiple DRAM dies in one package footprint and uses TSVs to connect them. But each added layer raises manufacturing and packaging demands: dies must be thin enough for the target stack, connections must bond reliably, and the assembled stack must be managed for thickness and warpage. Temporary carrier support helps make backside processing possible after frontside bumping.
HBM also faces a design trade-off inside each memory die. SK hynix’s 2024 HBM3E design article says TSV signals use area in peripheral circuits and can constrain scaling. In that article, the company gives 20–30% as a typical share of memory-product area occupied by peripheral circuits; this is a company-published general figure, not an independently validated industry-wide measurement.
What manufacturer examples show
Product announcements illustrate how process choices support a particular target, but manufacturer claims should be read as dated, attributed figures rather than neutral comparisons. SK hynix announced a 12-layer HBM3E product in September 2024 with 36GB capacity and reported an operating speed of 9.6 Gbps. The company said it made the DRAM dies 40% thinner to fit 12 layers within the thickness of its previous eight-layer product. It also reported 10% higher heat-dissipation performance for its Advanced MR-MUF 12-layer HBM3E compared with the previous generation. These are SK hynix’s product claims, not independent benchmark results.
Samsung’s November 2024 HBM4 mechanical test vehicle page described a prototype intended to help customers prepare OEM assembly, pre-qualification, and thermal evaluation. Samsung said the planned production device would use advanced DRAM processing for the core and SF4x (4 nm-class) logic for its base die. That dated prototype description is not confirmation of current commercial availability.
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What is not established by public process descriptions
Public manufacturer explanations are useful for understanding the sequence, but they do not establish proprietary lithography recipes, process windows, defect-density data, yield figures, or a neutral ranking of suppliers’ current manufacturing methods. The SK hynix process explainer documents one via-middle flow; it should not be treated as proof that every supplier uses the same sequence.
Real approaches can vary in where TSVs enter the process, whether dies or wafers are bonded, whether mass reflow or thermocompression is used, how temporary carriers are handled, and how underfill or molding is applied. Without comparable supplier data for factors such as throughput, yield, warpage, and thermal performance, those alternatives cannot be ranked reliably.
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