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Choose NVIDIA when CUDA compatibility, broad framework support, and deployment flexibility are the constraints you cannot compromise on. Choose AMD Instinct when an open ROCm stack, high-memory accelerators, or a second supply path matters and your team can test software on the exact MI300 system. Choose Google TPU when dense tensor operations compile cleanly with XLA, your team is comfortable with JAX or PyTorch/XLA, and Google Cloud is an acceptable operating environment.
There is no universal winner. Memory capacity, interconnect topology, precision, batch size, software maturity, availability, and the cost of keeping the hardware busy usually matter more than a peak-FLOPS number. The practical choice is the platform that completes your target training step or generates a token at the lowest acceptable engineering and infrastructure cost.
What the three platforms are
NVIDIA data-center GPUs
NVIDIA GPUs are general-purpose parallel processors with a mature AI software path. The H200 is a Hopper data-center GPU with 141 GB of HBM3e and 4.8 TB/s of memory bandwidth. NVIDIA’s HGX component documentation lists the B200 at 180 GB of HBM3e per GPU and describes eight-GPU HGX systems. CUDA supplies the programming model and core libraries; TensorRT, Triton, and NVIDIA AI Enterprise add optimized inference, kernel development, and supported deployment options. Exact support still depends on the framework, driver, CUDA release, and the model’s operators.
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AMD Instinct products, including the MI300 family, target AI and high-performance computing with high memory density and bandwidth. ROCm is an open software stack containing drivers, development tools, APIs, compilers, libraries, and runtimes. That openness can reduce dependence on one proprietary programming environment, but it does not make every CUDA application a drop-in replacement. Framework version, kernel coverage, collective communication, and monitoring must be checked on the specific MI300 configuration you plan to deploy.
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Google Tensor Processing Units
Google describes TPUs as “custom-developed, application-specific integrated circuits (ASICs) designed to accelerate machine learning (ML) and artificial intelligence (AI) workloads.” XLA compiles tensor programs to TPU TensorCores. Google Cloud currently documents TPU v5e, v5p, v6e (Trillium), and TPU7x (Ironwood). A TPU is therefore a tightly integrated service and compiler target rather than a general accelerator that you can install in any server.
Published specifications that are actually comparable
The figures below are vendor-published specifications, not a cross-platform benchmark. NVIDIA figures describe individual GPUs, while Google’s figures describe a TPU chip. System performance also depends on host processors, interconnect, software, parallelism, and utilization.
| Accelerator | Published compute figure | High-bandwidth memory | Memory bandwidth | What the figure represents |
|---|---|---|---|---|
| NVIDIA H200 | Not stated in the supplied product specification | 141 GB HBM3e | 4.8 TB/s | One Hopper data-center GPU |
| NVIDIA B200 | Not stated in the supplied HGX component specification | 180 GB HBM3e per GPU | Not stated in the supplied passage | One GPU in an HGX reference system; HGX systems can contain eight GPUs |
| AMD Instinct MI300 family | Not stated as one directly comparable single-card value | AMD emphasizes high density | AMD emphasizes high bandwidth | Qualitative claims from the official MI300 material; do not infer a ranking |
| Google TPU v5e | 197 BF16 TFLOPs | 16 GB HBM | 800 GiB/s | One TPU chip |
| Google TPU v6e (Trillium) | 918 BF16 TFLOPs | 32 GiB HBM | 1,638 GB/s | One TPU chip |
| Google TPU7x (Ironwood) | 2,307 BF16 TFLOPs | 192 GiB HBM | 7,380 GB/s | One TPU chip |
Do not compare a TPU chip with an eight-GPU server as if they were equivalent units. For a real design, compare the number of chips or GPUs required by the model, the communication fabric, host capacity, storage, and achieved throughput at your selected precision.
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How software changes the decision
CUDA: the lowest-risk default for existing code
CUDA is usually the safest choice when your stack already uses CUDA libraries, custom kernels, Triton code, TensorRT engines, or third-party packages that assume NVIDIA devices. It supports heterogeneous frameworks and unusual operators with fewer porting surprises. This advantage is operational as well as technical: debugging guidance, container images, profilers, and production integrations are widely available.
“Compatible” does not mean automatic. Confirm the CUDA toolkit, driver, framework build, GPU architecture, attention kernels, quantization path, and collective-communication library used by your application. A package that installs may still fall back to a slower implementation or fail at runtime for a missing operator.
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ROCm: a credible alternative when you validate the workload
ROCm can be an excellent fit for teams that value an open stack, want another procurement path, or are building software with portable kernel abstractions. The important question is not whether a framework has a ROCm package; it is whether your exact model uses supported kernels, collectives, profilers, and serving components on the MI300 system you will operate.
Plan a port rather than a package swap. Audit CUDA extensions and custom operators, replace unsupported APIs, test distributed collectives at the intended scale, and verify that monitoring and fault recovery expose the signals your operations team needs. Keep a known-good container and a rollback path while performance and correctness are being established.
XLA and TPU: compilation is part of the programming model
TPUs reward programs that present large, regular tensor computations to XLA. JAX is a natural fit, and PyTorch/XLA can work well when the model follows its supported execution patterns. Compilation, graph shape, input pipeline behavior, and sharding are part of performance engineering; changing a shape or inserting an unsupported operation can trigger recompilation or a CPU fallback.
Google warns that TPUs can be poor fits for frequent branching, custom operators executed on the CPU, and FP64-heavy scientific workloads. Those cases may need redesign, a fallback path, or a different accelerator. TPU use also creates a Google Cloud dependency, so account for its regions, quota, networking, identity, and release cadence before committing.
Match the accelerator to the workload
Large-model pretraining
Start with memory and interconnect, not nominal arithmetic throughput. Determine the model’s parameter, optimizer, activation, and checkpoint footprints at the chosen precision. Then measure how many devices are needed and whether the topology keeps them fed with data.
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- NVIDIA: a strong default for transformer training that depends on mature CUDA kernels, broad distributed-training libraries, or frequent architecture changes.
- AMD: attractive when MI300 memory density and an alternative supply path reduce the number of devices or procurement risk, provided ROCm collectives and kernels pass your tests.
- TPU: compelling when the training graph is regular, XLA compilation is stable, and Google Cloud capacity is available for the required pod shape.
Measure completed training tokens per dollar and per wall-clock hour, including failed jobs, checkpoint time, input processing, and reserved capacity that sits idle.
Fine-tuning and experimentation
Fine-tuning often involves changing batch sizes, sequence lengths, adapters, quantization, and data pipelines. NVIDIA generally minimizes friction for rapidly changing experiments. AMD can work well when your framework and kernels are already ROCm-tested. TPUs require enough shape stability to amortize compilation and may be less convenient for ad-hoc custom operations.
Inference and serving
Inference is sensitive to latency targets, batch variability, memory for weights and key-value cache, and the serving framework. NVIDIA’s TensorRT and Triton ecosystem is useful when you need many model architectures, dynamic batching, or mixed deployment targets. AMD is viable when your serving stack has production-tested ROCm paths and the MI300 memory profile lowers device count. TPU serving can be efficient for stable, high-volume, compiled graphs, but account for compilation, autoscaling behavior, and Google Cloud placement.
Scientific and HPC workloads
Inspect precision requirements before selecting an accelerator. TPU guidance specifically flags FP64-heavy workloads as a poor fit. NVIDIA and AMD GPUs offer broader scientific-computing ecosystems and custom-kernel options, but you still need to verify the libraries and numerical behavior used by your code. Branch-heavy algorithms and irregular memory access generally favor a more programmable GPU path over a narrowly optimized tensor graph.
Cost: compare useful work, not a headline rate
Google Cloud publishes transparent US on-demand chip-hour prices checked on October 20, 2026: $1.20 for TPU v5e, $4.20 for TPU v5p, $2.70 for Trillium, and $12.00 for Ironwood. Region and commitment change those prices. They are prices for one TPU chip-hour, not for a complete VM or training system.
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| Google Cloud TPU option | US on-demand price checked 2026-10-20 | Important qualification |
|---|---|---|
| TPU v5e | $1.20 per chip-hour | Region and commitment can change the rate; host and other services are extra |
| TPU v5p | $4.20 per chip-hour | Region and commitment can change the rate; host and other services are extra |
| TPU v6e (Trillium) | $2.70 per chip-hour | Region and commitment can change the rate; host and other services are extra |
| TPU7x (Ironwood) | $12.00 per chip-hour | Region and commitment can change the rate; host and other services are extra |
NVIDIA and AMD enterprise accelerator prices are normally configuration- and channel-specific; there is no universal US street price in the cited product material. For a fair comparison, include the server or VM, host CPU and memory, storage, networking, interconnect charges, software support, power, cooling, reservations, and idle time.
Use a workload metric such as:
- training: dollars per million completed tokens at a target loss, including checkpoint and evaluation time;
- inference: dollars per million generated tokens at a specified latency percentile and batch distribution;
- fine-tuning: dollars per successful run, including compilation, data preprocessing, and failed or retried jobs.
A lower chip-hour rate can lose if the model needs more chips, compiles repeatedly, transfers data across regions, or leaves capacity unused.
A practical selection procedure
- Freeze the workload definition. Record model architecture, parameter count, sequence length, precision (BF16, FP8, FP16, or FP64), batch-size range, target latency or training schedule, dataset location, and checkpoint frequency.
- Calculate memory headroom. Include weights, optimizer states, activations, attention key-value cache, framework overhead, and a safety margin. If the model does not fit, evaluate sharding and communication before looking at peak FLOPs.
- Inventory software dependencies. List CUDA-only extensions, ROCm support, XLA compatibility, custom operators, quantization libraries, profilers, and serving components. Mark each as production-ready, experimental, or unavailable on each platform.
- Map the topology. Confirm GPU-to-GPU or TPU-to-TPU links, host bandwidth, pod or server shape, storage throughput, and the communication pattern required by data, tensor, and pipeline parallelism.
- Run an equivalent pilot. Use the same data, precision, optimizer, sequence lengths, checkpoint policy, and warm-up rules. Record achieved throughput, step-time variance, memory use, compilation time, failure rate, and operator fallbacks.
- Normalize total cost. Add accelerator, host, storage, networking, software, support, and utilization costs. Use the same useful-work metric for every candidate.
- Stress operational risks. Test restart and checkpoint recovery, upgrades, observability, quota or procurement lead time, and capacity at the scale you actually need.
- Choose a primary and a fallback. Document the minimum software versions, container digest, kernel set, and acceptance thresholds so a supply or capacity change does not become an emergency rewrite.
What to test in an NVIDIA-to-AMD migration
- Build the application with the supported ROCm compiler and framework release rather than assuming a CUDA container will translate.
- Exercise every custom CUDA extension, fused attention path, quantization kernel, and data-loader operation.
- Measure collective operations at the planned node count; single-device tests can hide scaling bottlenecks.
- Compare numerical tolerances and convergence, not just speed. A silent precision or kernel change can invalidate a training run.
- Verify production telemetry, health checks, container images, and automated recovery on MI300 hardware.
If one critical operator has no acceptable ROCm implementation, retaining NVIDIA for that service or redesigning the operator may cost less than forcing a full migration.
What to test before committing to TPUs
- Compile the complete training or serving graph, including preprocessing boundaries and control flow.
- Check whether dynamic shapes cause repeated compilation and whether the input pipeline keeps the TPU supplied.
- Identify CPU fallbacks and custom operations; quantify their synchronization and transfer cost.
- Validate sharding, checkpoint format, restart behavior, and the exact TPU slice or pod shape available in your region.
- Confirm quota, reservation, identity, network, storage, and monitoring requirements in Google Cloud.
A TPU pilot should report compilation time separately from steady-state execution. A short benchmark that measures only already-compiled steps can substantially understate real job cost.
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Common decision mistakes
Ranking by peak FLOPs alone
Peak arithmetic does not reveal whether the model is memory-bound, communication-bound, compiler-limited, or waiting on input. Memory capacity and interconnect frequently determine whether a large model fits and scales.
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Comparing unlike pricing units
A chip-hour, a GPU-hour, an eight-GPU server, and a complete VM are different units. Normalize the hardware and service envelope before publishing or approving a cost comparison.
Assuming framework labels guarantee performance
“Supports PyTorch” or “supports JAX” says little about custom operators, kernels, collectives, dynamic shapes, or production serving. Test the exact model and versions.
Ignoring availability and lock-in
A theoretically efficient design is not useful if the required region, quota, server shape, or supply channel is unavailable. TPU use concentrates infrastructure dependence in Google Cloud; CUDA and ROCm choices affect software and procurement portability in different ways.
Decision guide
| Your priority | Most likely starting point | Condition to verify |
|---|---|---|
| Existing CUDA code, many third-party packages, varied models | NVIDIA GPU | Driver, CUDA, framework, and kernel version compatibility |
| High memory density plus an open alternative stack | AMD Instinct MI300 | ROCm operator coverage, collectives, observability, and team expertise |
| Stable dense tensor graph and JAX or PyTorch/XLA expertise | Google TPU | XLA compilation, sharding, quota, region, and Cloud dependency |
| FP64-heavy or branch-heavy scientific code | Usually a GPU platform | Required numerical libraries and precision performance |
| Lowest measured cost per useful token | Whichever wins your pilot | Include host, storage, networking, compilation, failures, and utilization |
Bottom line
NVIDIA is the safest general-purpose answer for CUDA-centered AI software and mixed, changing workloads. AMD Instinct is a serious choice when ROCm compatibility is proven and memory capacity, openness, price diversification, or supply resilience has strategic value. Google TPU can be exceptionally well matched to large, regular tensor programs that compile efficiently through XLA, but it demands Google Cloud capacity planning and a willingness to design around the compiler. Run a controlled pilot on the target model before treating any vendor specification or chip-hour price as a performance or cost verdict.
Quick Recap
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