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A 40G MACsec FPGA design is a system integration target, not just an encryption block: it combines MACsec frame processing and AES-GCM datapath with an Ethernet MAC/PHY, the FPGA’s transceiver interfaces, clocking, and a control and key-management path. Several vendor offerings address parts of that design, but their throughput and compatibility claims describe different products and conditions. Choose a route only after confirming it fits your FPGA and interface, sustains the traffic you need, and has suitable verification and support.
What a 40G MACsec core needs to do
MACsec, defined by IEEE 802.1AE, protects Ethernet frames at Layer 2 with confidentiality and integrity/authentication. In a typical design, frames pass through MACsec processing that handles security-related frame fields and integrity checks, while an AES-GCM datapath performs cryptographic operations. Security associations, packet-number state, configuration, and keys also need to be managed. The cited product material does not define one universal block partition or say that every core includes all of these functions.
Separate the design into two connected paths so that product boundaries are clear before implementation:
- Data path: ingress and egress Ethernet frames, MACsec field handling, AES-GCM processing, and the state needed to apply the selected security association.
- Management path: configuration, security-association and packet-number handling, and the interface through which trusted software or another control function provisions keys. Do not assume that a datapath IP core also provides a complete key-management system.
The Ethernet side is a separate integration concern. A 40GbE MAC/PCS/PMA and transceiver connection move frames between the FPGA and the physical link; a MACsec core secures those frames. Confirm the attachment point and interfaces for the actual components rather than treating “40G Ethernet” and “40G MACsec” as interchangeable IP labels.
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What the documented options establish
The available product descriptions show several possible routes, not a performance ranking. Their claims come from vendors or product documents, not from independent testing of a complete 40G FPGA system.
| Route | Documented evidence | What to confirm for your design |
|---|---|---|
| Xiphera high-speed MACsec AES-GCM, listed by Microchip | The listing names 10G/25G/40G and IEEE 802.1AE-2018. Microchip’s IP Core Tool gives 100,617 4-input LUTs as the stated requirement for a typical PolarFire implementation; the listing describes pure RTL and relevant test vectors. | Exact supported device and configuration, measured throughput for that configuration, interface and latency details, test-vector scope, and current license and support terms. |
| Algotronix 40G MACsec core | A preliminary datasheet dated September 2015 states “40 Gbit/sec with 324MHz clock,” describes 256-bit keys, and says the design is optimized for Xilinx devices. The throughput and clock figure are vendor claims for that design, not independent benchmark results. | Whether it is currently sold and supported; supported devices, resources, standard revision and features; and traffic conditions behind the stated rate. |
| Altera MACsec FPGA IP with Symmetric Cryptographic Accelerator (SCA) | The product page describes configurable soft IP for IEEE 802.1AE-2018 and lists GCM-AES and XPN forms. It claims 100 Gbps full-duplex line rates when using SCA in select Agilex 7 F-series and I-series devices. | Whether the target is one of the supported devices, how the MAC/PHY attaches, and the configured resources, license, and throughput at the intended operating point. |
| Fraunhofer IPMS MACsec controller | A document surfaced from approximately 2023 describes IEEE 802.1AE-2018 and 802.1AEbw, AES-GCM/XPN options, and FPGA/ASIC platform independence. | 40G throughput on the selected FPGA, synthesis results, current version, interfaces, and license. |
| MACOM S12611 PHY | The product page lists MACsec and XPN features and supports 3x40GE or 1x100GE configurations. This is a PHY product route, not an FPGA MACsec IP core. | Availability, the complete datasheet, and whether its architecture fits better than an FPGA-based implementation. |
These distinctions matter when interpreting figures. For example, the Altera claim is explicitly conditional on SCA in select Agilex 7 devices; it does not establish that any Altera FPGA plus any MACsec core will achieve that rate. Likewise, Microchip’s listed LUT count is a typical PolarFire resource figure, not a universal requirement for other devices or configurations. The Xiphera listing’s broad “100s of Gbps” wording should not be read as a measured result for a particular 40G build.
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Choose a system architecture before selecting the core
Check the FPGA and accelerator path
Start with the exact FPGA family, part, speed grade, and available hard IP. Xiphera’s cited resource example is specific to a typical PolarFire implementation. Altera’s SCA-dependent throughput claim applies only to select Agilex 7 F-series and I-series devices. Those are vendor-specific architectures; they do not imply common resource needs or portability across FPGA families.
Define the Ethernet attachment point
Altera’s separate 40G Ethernet product describes MAC/PHY behavior and interfaces to copper or optical modules. That is evidence that the Ethernet interface layer is distinct from MACsec processing. Before pairing an Ethernet IP block and a security core, establish where frames enter and leave MACsec, the interface width and clocking on that boundary, and which component owns any required adaptation. Product names alone do not establish compatible interfaces.
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Decide what the security feature set must support
The cited offerings refer to combinations of GCM-AES-128/256 and XPN variants, but the evidence does not establish a single feature set common to all products. Specify the required cipher suite and key length, whether XPN is needed, the number of simultaneous security associations, and the relevant packet-number and rekey behavior. Ask vendors to identify supported options in the exact core version and configuration you would license.
Choose where control and keys live
Map the trust boundary before wiring the management interface. Identify which software or trusted subsystem provisions keys, configures security associations, and handles lifecycle events, and how that control path communicates with the datapath. Do not infer that a core’s cryptographic engine supplies key management or a complete host software stack; confirm the delivered RTL, drivers or APIs, examples, and responsibilities in writing.
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How to evaluate a 40G implementation
Use a written acceptance target that covers the whole frame path, not just the cipher block. In particular, ask vendors to explain how their throughput figure is defined and measured. A 40G label does not by itself tell you whether a result is sustained for the traffic mix you care about, whether it is per direction or aggregate, or whether it includes all MACsec processing and interface overhead.
- Rate and traffic: Require the target device and core configuration, sustained rate, full-duplex or per-direction definition, supported frame sizes, and treatment of minimum-size frames and back-to-back traffic.
- Latency and buffering: Request latency through the complete processing path and any buffering or backpressure constraints that affect your application.
- Implementation fit: Obtain resource use and timing results for the exact FPGA, clocking, interfaces, and enabled features—not a family-level estimate alone.
- Security functionality: Confirm standard revision, cipher suites and key sizes, XPN support if needed, security-association capacity, and packet-number handling.
- Verification evidence: Ask what test vectors, protocol tests, interoperability evidence, and compliance results are included. A vendor’s reference to a standard or test vectors is not, by itself, proof of certification or of a complete system passing your acceptance tests.
- Ownership and support: Clarify RTL or other deliverables, license scope, current availability, update policy, support term, and which party owns integration and maintenance.
A practical build-and-verify sequence
- Freeze the target: Record the FPGA part, board-level Ethernet interface, intended line rate and directionality, required security features, and operating environment.
- Shortlist compatible components: Match a MACsec core to the exact device and its MAC/PHY path. Get interface specifications and configuration-specific resource and performance evidence from each vendor.
- Draw the boundaries: Document frame ingress and egress, MACsec processing, clock domains, reset behavior, flow control, management interface, and key provisioning responsibilities.
- Build a resource and timing estimate: Include the Ethernet IP, MACsec datapath, buffers, management logic, and any required accelerators. Treat published numbers as estimates only when they refer to a different configuration.
- Verify functions independently and together: Test the security core with its supplied vectors where available, then verify the integrated frame path, configured security associations, traffic conditions, and error handling on the intended platform.
- Validate on hardware: Measure sustained bidirectional behavior, latency, and resource/timing results on the selected device and interface before treating a vendor headline rate as an achieved system rate.
When a PHY route may be more appropriate
MACOM’s S12611 is listed as a PHY supporting 3x40GE or 1x100GE configurations with MACsec and XPN-related features. It is worth evaluating if the design goal is better served by a dedicated PHY architecture than by integrating FPGA MACsec IP. It should not be compared as though it were a portable RTL core: obtain the complete datasheet and determine how it fits the rest of the system.
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What is and is not established
The vendor material available on 2026-10-04 establishes that named MACsec-related products and architectures are documented, including one listing that explicitly names 40G and one preliminary 2015 datasheet with a 40 Gbit/s claim. It does not establish current availability or licensing, a verified end-to-end 40G FPGA implementation, comparative performance, timing closure, or compatibility among products. Treat those as procurement and engineering checks for the specific configuration, not as settled properties of the category.
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