To add a domain-specific accelerator to a RISC-V design, first check whether the workload already fits a ratified standard extension—especially the vector or cryptography extensions. If it does not, choose between vendor-specific custom instructions for compact, frequent operations and an attached accelerator for larger, asynchronous work. The right choice depends as much on data movement, software support, operating-system needs and portability as on the accelerator’s compute throughput.
Choose the least specialized interface that fits the workload
Start by describing the work the accelerator will do: its inputs and outputs, how often it runs, how much data it processes, whether operations can be batched, and whether it needs private state or memory. Then compare that workload with the standard RISC-V extensions before defining a new interface.
Use vector instructions for regular data-parallel work
The ratified RISC-V V extension is the portable starting point when a kernel applies similar operations across many data elements. It adds 32 vector registers and seven unprivileged control and status registers: vstart, vxsat, vxrm, vcsr, vtype, vl and vlenb. The V specification also anticipates future vector extensions with richer functionality for particular domains.
Vector code is most attractive when the work maps naturally to vector lanes and portability across conforming implementations matters. Before committing to it, assess the implementation’s vector length, element widths, masking needs and memory bandwidth. A kernel with little parallel work may not benefit enough to offset setup and data-movement costs.
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Use ratified cryptography extensions for supported algorithms
For supported cryptographic workloads, standard scalar or vector cryptography extensions can avoid creating a private instruction set. The scalar cryptography specification is a separate standard suited to scalar implementations and smaller cores. The vector cryptography specification defines domain-specific instructions and identifies dependencies on Zve32x or Zve64x for several subsets.
That specification requires data-independent execution latency for the cryptography-specific instructions in Zvkned, Zvknh[ab], Zvkg, Zvksed and Zvksh. It also distinguishes supporting extensions including Zvbb, Zvkb and Zvbc. Check the exact extension dependencies and algorithm coverage against the intended implementation rather than treating “vector crypto” as one indivisible feature.
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Define a custom extension only for a real gap
RISC-V permits vendor-specific non-standard extensions in custom encoding space. The Unprivileged ISA introduction states: “Custom encodings shall never be used for standard extensions and are made available for vendor-specific non-standard extensions.” A custom instruction can expose a small, frequent operation with low invocation overhead, but its encoding and software support are specific to the implementation.
Custom instructions are less suitable when a job needs long command sequences, substantial local storage or asynchronous execution. Those needs can make a coprocessor or a separately managed accelerator a cleaner fit than forcing the entire operation through instruction encodings.
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Understand the main integration patterns
A RISC-V system can integrate specialized computation in more than one place. The choice determines how software invokes it, how data reaches it and what the operating system must manage.
+--------------------- RISC-V system ----------------------+ | | | +-------------+ +-------------+ +----------------+ | | | Scalar core |-->| Vector unit | | Custom-function| | | | | | | | unit (optional)| | | +------+------+ +------+------+ +-------+--------+ | | | | | | | +-----------------+------------------+ | | | | | +------+-------+ | | | Memory system| | | +------+-------+ | | | | | +---------+----------+ | | | Optional accelerator| | | | fabric / coprocessor| | | +--------------------+ | +----------------------------------------------------------+
This is a conceptual arrangement, not a required RISC-V implementation. A vector unit or custom-function unit may be tightly coupled to the core; an attached accelerator may instead use a system interconnect and its own control and memory resources. The actual data paths, sharing model and synchronization mechanism are design choices.
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Tightly coupled custom instructions
The core issues an instruction that invokes a specialized operation through the implementation’s custom extension. This is a good candidate when the operation has a compact operand interface and is called often enough for low dispatch latency to matter. It also lets software express the operation directly, but requires vendor-specific compiler or assembler support and an explicit plan for binary compatibility.
Coprocessor or accelerator interface
A coprocessor or attached accelerator can accept larger jobs and perform work asynchronously, which can suit long-running kernels or engines with local storage. In exchange, software must submit work and coordinate completion; queues, interrupts or synchronization can add overhead. Data may need to move through shared memory, a cache-coherent path, DMA or a scratchpad, depending on the design.
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Host platform with accelerator plug-in
A host can manage one or more accelerators through a system-level interface. The published Cheshire work describes a lightweight, Linux-capable RISC-V host platform for domain-specific accelerator plug-in, with an application-class host coordinating compute-specialized multicore accelerators. This pattern is relevant when Linux, virtual memory, drivers or asynchronous control are part of the requirements. It is an implementation example, not evidence that every accelerator should use the same architecture.
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| Decision factor | Standard vector or crypto extension | Custom instruction | Attached accelerator |
|---|---|---|---|
| Portability | Ratified extension code is the more portable route across conforming implementations that support the relevant extension. | Vendor-specific code path; portability requires fallback code or implementation-specific dispatch. | Depends on the accelerator interface, driver and software abstraction; not established as one common interface by the cited examples. |
| Invocation pattern | Instructions execute in the core’s architectural model; vectors suit data-parallel operations. | Direct instruction invocation can keep dispatch overhead low for compact operations. | Can batch or run longer jobs asynchronously, with queueing and synchronization costs. |
| Data movement | Uses the implementation’s vector and memory paths; bandwidth and setup can limit gains. | May consume core-visible operands, but interface capacity constrains how much work can be expressed per instruction. | May require DMA, scratchpad access or shared-memory transfers; quantify bytes moved per operation. |
| Toolchain work | Uses existing compiler paths such as vector intrinsics or auto-vectorization where supported. | Needs assembler/compiler exposure, often backend changes, scheduling rules and simulator/model support. | Needs a software submission and completion path, commonly including runtime or driver support. |
| OS and architectural state | Follow the specified extension behavior and implementation’s support for the relevant execution environment. | Any added architectural state needs a context-switch plan; software tools must understand the instruction. | Plan memory protection, interrupts, device state and coherency or sharing requirements, especially for Linux. |
| Security and determinism | The specified vector cryptography instructions have a data-independent-latency requirement; other behavior depends on the extension. | Document and validate the custom operation’s timing and side-channel behavior. | Define isolation, access control and timing behavior for the accelerator and its data paths. |
| Area, power and throughput | Measure on the intended implementation and workload; no common cross-design values are established. | Measure the custom unit and its effect on the core and system for the target workload. | Measure the accelerator, interconnect, memory traffic and host overhead together for the target workload. |
The table describes architectural trade-offs, not guaranteed performance rankings. There is no single cross-design benchmark here that establishes a universal speedup, area or energy advantage. Published results should be interpreted only for the implementation, workload and measurement conditions that produced them.
A practical design process
- Characterize the kernel. Record operation mix, data sizes, parallelism, invocation frequency, latency targets and whether jobs can run asynchronously. Estimate data transferred per operation as well as compute.
- Check standard support. Determine whether V, scalar cryptography or vector cryptography extensions cover the work. Confirm the exact extension subset and dependencies in the relevant RISC-V specification.
- Select the invocation model. Prefer vector instructions for regular lane-parallel work; consider a custom instruction for a compact frequent operation; consider a coprocessor or host-attached accelerator for large, stateful or asynchronous jobs.
- Specify the data and state contract. Decide where operands and results reside, whether memory is shared or transferred, how private state is represented, and how completion, errors and interrupts are reported.
- Budget software support before RTL. For a custom instruction, plan compiler or intrinsic exposure, assembler syntax, scheduling, simulation and formal-model support. For an attached accelerator, define the submission API, driver or runtime, memory protection and synchronization behavior.
- Measure end-to-end behavior. Include dispatch, setup, data movement, synchronization and operating-system overhead—not just the accelerator’s compute time. Compare against a standard-extension implementation on the same workload.
- Plan compatibility and security. Decide how software detects the feature and falls back when unavailable. Specify context-switch behavior for added state and assess timing leakage or isolation risks for the target use.
Examples show possibilities, not universal results
The 2025 preprint “Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing” presents a RISC-V SoC integrating custom DSP accelerators for edge workloads. It demonstrates one implementation direction; its area, timing and energy measurements apply to that paper’s reported experiments, not to RISC-V accelerators generally.
The Cheshire host-platform paper illustrates a different problem: coordinating specialized multicore accelerators from a Linux-capable RISC-V host. Together, the examples show why “add an accelerator” can mean either extending the processor’s instruction behavior or designing a host-and-device system. Neither establishes a universal winner.
What to document for a usable custom extension
A hardware block alone is not a complete extension. To make a custom design usable and maintainable, document the instruction or device interface and provide a software path that makes its behavior explicit.
Quick Recap
- Define operand, result, exception and completion semantics, including any added architectural state.
- Provide compiler intrinsics or a driver/runtime interface, plus assembler and simulator support as appropriate.
- Specify how programs detect availability and what happens on systems without the feature.
- Describe context switching, interrupts, memory protection, coherency and security behavior required by the chosen integration.
- Publish workload-specific measurements that include data movement and software overhead alongside compute throughput.
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