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Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallA 555 and CD4060B make a practical long-delay timer: the 555 generates a clock, and the CD4060B divides it to create much slower output transitions. This approach avoids the very large resistance or capacitance a 555-only circuit may need for long intervals. The example below is a nominal hobby circuit, not a precision or safety timer.
How the 555 and CD4060B timer works
The two ICs have separate jobs. In astable mode, the 555 repeatedly charges and discharges a capacitor, producing a square-wave clock. The CD4060B counts those clock pulses through 14 ripple-counter stages and makes available divided-down outputs. A selected output can control an indicator or, through a suitable driver, a load.
The CD4060B also has an oscillator section, but this design uses the 555 as the clock source. Feed the 555 output to the CD4060B clock input specified in the datasheet; do not add a separate RC or crystal oscillator to the CD4060B oscillator pins at the same time. Pin labels and package details should be checked against the exact part’s datasheet.
Example circuit and components
Use this as a starting point for a breadboard circuit. Choose a 555 variant and supply voltage within the ratings of both ICs; “555” devices are not electrically identical.
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- One NE555 or CMOS TLC555 timer
- One CD4060B, such as the through-hole CD4060BE for breadboard use
- RA = 10 kΩ and RB = 68 kΩ
- C = 10 µF timing capacitor; observe polarity if it is electrolytic
- Approximately 10 nF from the 555 control-voltage pin to ground
- One 100 nF ceramic bypass capacitor close to each IC’s supply pins
- Optional 10–100 µF bulk supply capacitor
- A pull-down resistor and pushbutton for manual CD4060B reset
- An LED with series resistor, or a separate transistor/MOSFET driver for a larger load
Connect both ICs to a common supply and ground. For the standard 555 astable connection, join trigger and threshold, connect RA from supply to the discharge node, connect RB from the discharge node to the trigger/threshold node, and connect the timing capacitor from that joined trigger/threshold node to ground. Hold the 555 RESET input high during normal operation and take the clock from its output. Connect that output to the CD4060B’s clock input as specified by the exact device datasheet. Hold the CD4060B RESET low for normal counting.
Use the TI CD4060B datasheet for its package pinout, clock and oscillator connections, electrical limits, and output mapping. The exact output pin must be identified from the package drawing rather than inferred from another 4060-family part.
Calculate the timing
Estimate the 555 clock
For the standard astable arrangement, the approximate frequency is:
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f ≈ 1.44 / ((RA + 2RB) × C)
With RA = 10 kΩ, RB = 68 kΩ, and C = 10 µF, the estimate is about 0.986 Hz, or a clock period near 1.01 seconds. TI gives the astable timing relationships as tH = 0.693(RA + RB)C, tL = 0.693RB C, and T = 0.693(RA + 2RB)C in its TLC555 datasheet. Actual timing depends on the selected 555 and components.
Select a divider output
For a counter stage n, the complete output period is approximately 2n input clocks. The approximate time to the first transition from reset is half that: 2n−1 clocks. Thus, a full output period is not the same as a one-shot delay to the first edge. Whether a load activates at that first edge also depends on which edge and output level the driver uses.
At the example clock frequency of approximately 0.986 Hz, these are calculated nominal complete output periods, not measured results:
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| Output | Division | Approximate full period |
|---|---|---|
| Q4 | 16 | 16.2 seconds |
| Q5 | 32 | 32.5 seconds |
| Q6 | 64 | 64.9 seconds |
| Q7 | 128 | 129.7 seconds |
| Q8 | 256 | 259.6 seconds |
| Q9 | 512 | 519 seconds |
| Q10 | 1,024 | 1,038 seconds, about 17.3 minutes |
| Q12 | 4,096 | 4,152 seconds, about 69.2 minutes |
| Q13 | 8,192 | 8,304 seconds, about 2.31 hours |
| Q14 | 16,384 | 16,617 seconds, about 4.62 hours |
The CD4060B does not expose every counter stage; the listed outputs are Q4–Q10 and Q12–Q14. To change the interval, adjust the 555 frequency using RA, RB, or C, or choose another available output. For a desired complete output period, estimate f ≈ 2n/T; for a desired first transition, estimate f ≈ 2n−1/t.
Reset and startup behavior
The CD4060B RESET is active high: a brief high pulse clears the count, while low permits normal counting. For a manual reset, connect a pushbutton from RESET to the positive supply and a pull-down resistor from RESET to ground. A power-on reset capacitor may be added, but the reset must produce a sufficiently clean pulse; a slow or noisy edge can leave startup behavior uncertain. The 555 RESET is active low, so keep it high if unused rather than leaving it floating. TI describes the TLC555 reset behavior on its product page.
Connect an indicator or load safely
A CD4060B output is a logic signal, not a general-purpose power output. An LED needs a series resistor. A transistor base needs a base resistor; a logic-level MOSFET should have an appropriate gate resistor and gate pull-down. Check the output voltage and current limits in the exact device datasheet before connecting any load directly.
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For a DC relay, use a transistor or MOSFET driver, a flyback diode across the coil, and a supply arrangement that prevents coil current from disturbing the logic supply. Motors, solenoids, and lamps also require appropriately rated drivers. Never connect mains voltage directly to a breadboard timer; mains switching requires suitable isolation, ratings, enclosure, and wiring practices.
Build and test in stages
- Wire the 555 astable network, supply, ground, reset, control-pin capacitor, and bypass capacitor. Verify orientation and pin numbering.
- Measure the 555 output with an oscilloscope or frequency counter. Confirm a repeating waveform near the calculated frequency before connecting the divider.
- Connect the 555 output to the CD4060B clock input and share ground. Keep RESET low after applying a brief high reset pulse.
- Probe a low-order available output first. Confirm that successive stages divide the signal by approximately two.
- Move to the intended higher-order output and allow enough time for its first transition. Add the driver and load only after the logic stage counts reliably.
Troubleshooting
The 555 does not oscillate
- Check IC orientation, pin numbering, common ground, supply decoupling, and the timing-capacitor polarity.
- Confirm trigger and threshold are joined, the discharge pin is at the RA/RB junction, and RESET is not held low.
- Check for a timing resistor too large for the capacitor’s leakage and the chosen 555.
The CD4060B output stays fixed
- Verify the 555 waveform first, then confirm the correct CD4060B clock pin and package mapping.
- Check that RESET is low during counting and that the IC has the correct supply and ground connections.
- Ensure unused control inputs are not floating, and verify that the selected output exists on that package.
- Allow for the actual divider interval; a high-order output may not change during a short bench check.
The timing appears doubled, halved, or inaccurate
- Check whether the measurement is a full output cycle or just the first edge after reset.
- Confirm the 555 frequency, selected counter stage, output pin, and whether rising and falling edges are being counted.
- Allow for resistor tolerance, electrolytic-capacitor tolerance and leakage, 555 variation, supply and temperature changes, breadboard leakage, and poor decoupling.
A relay causes chatter or resets
Do not draw relay-coil current from the logic output. Add a driver and flyback diode, and check supply sag, grounding, and decoupling; switching current can disturb the counter even when the divider wiring is correct.
Accuracy and alternatives
The calculated periods are nominal. An electrolytic timing capacitor, especially, can vary substantially because of tolerance and leakage; resistor tolerance, temperature, supply conditions, and the 555’s behavior add further error. This circuit suits hobby timing, blinking, and sequencing, but not precision clocks, medical timing, safety timers, or certified control systems.
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A CMOS TLC555 can be preferable to a bipolar NE555 where lower power and smaller timing currents matter. TI lists TLC555 operation from 2 V to 15 V and notes its high input impedance; check the exact device specifications before selecting a supply or load. The NE555 product page provides its own device characteristics, which should not be assumed interchangeable with TLC555 behavior.
The CD4060B can also be used with its own RC or crystal oscillator, reducing the IC count; a crystal can improve stability, but its frequency and available divider stages still need to be chosen for the intended interval. A microcontroller offers programmable one-shot timing, while an RTC is more suitable for clock/calendar timing. For these alternatives, verify the specific device’s supply, pinout, reset, and output requirements rather than assuming other 4060-family parts match the CD4060B.
Quick Recap
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