On Cortex-M, a smaller priority number means a more urgent interrupt: priority 0 is the highest urgency. If an interrupt calls a FreeRTOS FromISR function, its priority must also be at or below the urgency allowed by the selected FreeRTOS port—in numeric terms, equal to or greater than the configured syscall threshold. The exact threshold depends on your MCU, port, implemented priority bits, and vendor-library conventions, so there is no safe universal number.
Understand Cortex-M priority numbers
Cortex-M peripherals and core exceptions use the NVIC exception model, which supports pending and active states, programmable priorities, and nested preemption. The number of interrupts and priority levels varies by core implementation and MCU; do not assume one fixed count for every Cortex-M device. SysTick is a core exception often used by an operating system.
Keep numeric priority distinct from urgency. A smaller numeric value has greater urgency and can preempt a less urgent interrupt. Priority 0 is the highest urgency; higher numbers are progressively less urgent. Arm author Miro Samek explains the reversed numbering in Arm’s guide to Cortex-M interrupt priorities.
Priority width and representation
Although NVIC priority fields are eight bits wide, a particular MCU implements only some of those bits, placed in the most-significant positions. Check __NVIC_PRIO_BITS in the device’s CMSIS header; the Cortex-M family name alone does not tell you the priority width.
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CMSIS NVIC_SetPriority(IRQn, priority) takes an unshifted logical priority and applies the register shift internally. A direct write to an NVIC priority register instead needs the hardware representation, with implemented bits in their register positions. For example, Arm’s NVIC_SetPriority(7, 6) illustration shows how a logical value is shifted for a device with three or four implemented priority bits; it is not a universal MCU setting.
Know which interrupts may call FreeRTOS
On FreeRTOS Cortex-M ports that use BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY marks a boundary associated with the interrupts masked by RTOS critical sections. An interrupt that calls an interrupt-safe kernel function ending in FromISR must be no more urgent than the permitted boundary. Because Cortex-M numbering is reversed, its numeric priority must be equal to or greater than the configured boundary. A more urgent interrupt—one with a smaller numeric value—must not call any FreeRTOS API, including a FromISR function.
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A common configuration mistake is leaving an API-calling interrupt at its reset or default priority of 0. That is the highest urgency, so it is above the API-calling boundary in the documented BASEPRI-based port. Set each interrupt’s priority explicitly before starting the scheduler.
Logical values versus FreeRTOS hardware values
Do not assume that a number passed to CMSIS and a FreeRTOS priority macro use the same representation. The documented FreeRTOS configuration values configMAX_SYSCALL_INTERRUPT_PRIORITY and configKERNEL_INTERRUPT_PRIORITY are already shifted into the implemented most-significant priority bits because the kernel accesses hardware directly. CMSIS priority APIs take unshifted logical values. Confirm the definitions and checks in the project’s FreeRTOSConfig.h, selected port, and vendor library before setting either value.
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BASEPRI cannot mask priority 0, so the FreeRTOS guidance for BASEPRI ports says configMAX_SYSCALL_INTERRUPT_PRIORITY must not be zero. This rule belongs to those ports and should not be copied blindly to a different port.
Configure priorities without guessing
- Identify the target. Find the exact MCU and Cortex-M core, then determine which FreeRTOS port the project uses.
- Check implemented bits. Read
__NVIC_PRIO_BITSfrom the selected device’s CMSIS header rather than assuming the width from the core family. - Inspect the port configuration. In
FreeRTOSConfig.hand the port source, locate the applicable syscall threshold and determine whether the port usesBASEPRI. Check how that port expects the threshold and kernel priority to be represented. - Classify each interrupt by API use. An interrupt that calls a permitted
FromISRAPI must be assigned a numeric priority equal to or greater than the configured boundary. An interrupt more urgent than the boundary must not call FreeRTOS. - Set priorities explicitly. Use the project’s CMSIS or vendor-library API with its expected logical or hardware value. Do this before starting the scheduler; do not rely on an interrupt’s default priority.
- Check grouping and diagnostics. Priority grouping can divide priority bits between preemption priority and subpriority. FreeRTOS recommends assigning the priority bits to preemption priority for its threshold logic; check vendor-library assumptions before changing the grouping. Enable available
configASSERT()checks during development, while treating them as diagnostics rather than proof that every configuration is correct. - Follow the ISR wake-up pattern. When an ISR wakes a task, use the appropriate
FromISRfunction and follow the yield-on-exit pattern documented for the selected API and port.
Account for core and port differences
The BASEPRI-based nesting guidance does not apply to Cortex-M0 and Cortex-M0+, which do not implement BASEPRI. Use the FreeRTOS documentation and configuration for the actual M0/M0+ port instead of carrying over rules from an M3/M4 or other BASEPRI port.
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Masking facilities also vary across Cortex-M cores. For example, Arm’s Cortex-M33 register summary describes PRIMASK as preventing activation of configurable-priority exceptions, BASEPRI as setting a minimum priority for exception processing, and FAULTMASK as masking all exceptions except NMI and, optionally, Secure HardFault. Those details describe Cortex-M33 capabilities; they should not be generalized to every Cortex-M core.
Why a universal threshold is unsafe
A numeric example can only be meaningful with the MCU’s implemented priority-bit count, the selected FreeRTOS port and its configuration, and any vendor-library conventions. CMSIS logical priority arguments, shifted NVIC register values, and FreeRTOS hardware-form macros are not interchangeable. Verify all three in the project rather than copying a threshold from another board or codebase.
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For the governing API and port rules, consult the FreeRTOS Cortex-M documentation. Arm’s Cortex-M interrupt latency guide discusses latency under stated processor and memory assumptions; latency figures should only be compared when those conditions match.
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