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AI can help generate semiconductor test patterns, but the right method depends on what you are trying to test. For manufacturing defects, AI can guide a conventional automatic test-pattern generation (ATPG) engine; for AI accelerators, optimization can select functional workloads or an LLM can generate validation tests. These approaches have different inputs, objectives, and proof requirements. None of the cited research establishes AI as a general drop-in replacement for scan design, fault modeling, deterministic ATPG, or validation.
First decide what “test pattern” means
A semiconductor test pattern is a set of input values or operations intended to expose a problem in a device. The phrase can refer to quite different artifacts: stimuli for detecting manufacturing defects, functional workloads that exercise an accelerator, or tests that check whether hardware behaves correctly. AI-generated tests are only meaningful when their objective is explicit.
In structural manufacturing test, ATPG analyzes a design and seeks input assignments that make a modeled fault observable at an output. AI may help choose or prioritize the search heuristics, while the ATPG engine performs the underlying search. In functional testing, patterns are valid operations or workloads chosen to exercise behaviors or stress hardware. In functional hardware validation, generated tests are checked against a design’s expected behavior and measured with design coverage. These are related tasks, but a workload that exercises a design is not automatically a manufacturing test pattern that detects a specified fault.
| Approach | Primary objective | Typical design relationship | What evidence should show |
|---|---|---|---|
| AI-guided structural ATPG | Find patterns that detect modeled manufacturing faults | Uses structural design information such as a gate-level netlist and scan context | Fault coverage for a stated fault model, plus search cost such as backtracks or runtime |
| Optimized functional test patterns | Select functional inputs or workloads that expose faults or stress hardware | May target a particular accelerator or behavior rather than a general netlist-based ATPG flow | Results for the specific hardware, fault target, and functional constraints |
| LLM-generated validation tests | Check accelerator behavior and increase design coverage | Can use a compiler or toolchain and coverage feedback to check generated tests | Test correctness and design coverage in the evaluated setting; not a substitute for manufacturing fault coverage |
What conventional ATPG does
ATPG, or automatic test-pattern generation, is an electronic-design-automation method for algorithmically producing input stimuli to detect manufacturing defects in digital integrated circuits. An ATPG system works from the circuit structure and a fault model. It searches for assignments that activate a fault and propagate its effect to an observable output, then produces patterns for the test flow.
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An IEEE technical overview describes gate-level netlists and scan-chain stitching information among the relevant inputs. Patterns can be delivered in formats such as STIL or ASCII WGL for use by automatic test equipment (ATE). The same overview describes validating patterns with fault simulation before tape-out. The exact input files and formats depend on the flow; the overview’s examples should not be read as a complete specification for every implementation.
This gives a useful way to understand the handoff: the design and test setup inform pattern generation; generated patterns are checked against the intended fault model; and validated pattern data can be prepared for the tester. A pattern file in a supported format is not, by itself, proof that the patterns detect the desired defects. The fault-simulation result and the defined fault list provide the relevant evidence about detection.
Fault models define what coverage means
- Stuck-at faults: model a net as fixed at logic 0 or logic 1.
- Transition faults: represent signals that arrive late, rather than making the intended transition on time.
- Path-delay faults: target timing behavior along a path through the circuit.
Coverage is the fraction of faults in a specified modeled fault list detected by at least one pattern. A coverage percentage is not self-explanatory: it needs the fault model, the fault-list denominator, and the evaluation context. Two percentages based on different models or fault lists are not directly comparable. A result for stuck-at faults does not by itself establish transition- or path-delay coverage.
For example, a stuck-at coverage figure describes detection within that stuck-at fault list; it does not mean the same patterns detect an equivalent fraction of timing-related faults. When a report gives a percentage, ask how many faults were considered, which model defined them, and whether the result is from a benchmark or the target design. Those details are essential whether the search was guided by AI or not.
Why scan and compaction matter
Scan design makes sequential circuits easier to test by allowing register contents to be shifted in and out. This reduces part of the sequential search problem to a more tractable combinational one. Scan is a design-for-test (DFT) choice, not something that an AI pattern generator can simply assume exists in the finished design.
Pattern count also affects deployment: more patterns can mean more test time. Pattern compaction combines patterns when coverage can be preserved, reducing the set applied to the device. A smaller pattern set is not automatically better if it loses required fault detection; compare count and cost alongside the coverage objective.
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Compaction is therefore a trade-off to measure, not a goal to optimize in isolation. A compacted set still needs to meet the intended coverage target, and the pattern count should be interpreted in the context of how the test is deployed. The 2023 accelerator paper also discusses compaction, but for its functional-image setting; do not assume its method or result transfers unchanged to scan ATPG.
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Where AI fits: three distinct approaches
1. Use machine intelligence to guide deterministic ATPG
A 2022 IEEE conference paper describes a PODEM ATPG system guided by combined heuristics. It combines distance to primary inputs and outputs, controllability-observability probabilities (COP), and SCOAP testability measures using principal component analysis (PCA). The intent is to guide the ATPG search more effectively than relying on one heuristic alone.
On the benchmark circuits evaluated in that paper, the authors report an order-of-magnitude reduction in total backtracks and reduced CPU time compared with implementations using a single heuristic. Those are experimental findings for the paper’s benchmarks and comparison; they are not a guaranteed speedup on another design, a production flow, or a different fault model. The method guides a deterministic ATPG process rather than proving that an AI model can replace the test engine.
When considering this kind of approach, separate the search guidance from the acceptance criteria. A heuristic can influence which choices the ATPG engine tries first, while the required output remains patterns that detect the modeled faults. The useful comparison is therefore not simply whether the AI component produced suggestions, but whether the complete flow achieved the target coverage and how much search effort it required against a meaningful baseline.
2. Optimize functional patterns for accelerator hardware
A 2023 IEEE paper proposes Bayesian optimization to generate functional test images for an AI inference accelerator. Its target is stuck-at faults in a systolic-array accelerator. The paper also discusses test-pattern compaction and error regularization to keep generated images functional-like. This is a specialized route: it is about useful functional images for a particular class of accelerator, not a generic netlist-to-scan-pattern replacement for structural ATPG.
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Functional-like constraints matter because a candidate that is mathematically useful for a fault objective may not be a suitable workload if it does not remain within the intended functional behavior. The paper’s discussion of error regularization and compaction is specific to its method and target. A team evaluating a similar idea should state what makes an image valid, what fault objective it targets, and how any reduced pattern set is checked.
A separate IEEE paper describes netlist-independent functional stress-pattern selection for AI hardware accelerators embedded in systems-on-chip (SoCs), particularly for burn-in stress. This is a different path from netlist-based structural ATPG. The indexed abstract does not provide enough detail to support broader claims about its performance or effectiveness.
3. Generate functional validation tests with an LLM
A 2026 IEEE paper proposes fine-tuning large language models (LLMs) to generate semantically correct tests for hardware accelerators. Its described flow checks tests with a compiler, uses design-coverage feedback, and reports a 33% improvement in design coverage in its evaluation. That figure is the paper’s reported result in its tested setting; it is not a general guarantee for other devices or toolchains.
This work concerns functional validation: checking tests for semantic correctness and monitoring how much design behavior they cover. It should not be described as conventional scan ATPG for manufacturing. Compiler acceptance and design coverage are useful checks for functional tests, but they are not equivalent to fault simulation against a structural fault list.
The checks serve complementary purposes. A compiler check can reject tests that are not valid for the relevant toolchain, while coverage feedback can indicate whether generated tests exercise additional design behavior. Neither check alone establishes manufacturing fault coverage. For a validation project, report the compiler/toolchain context and the coverage measure alongside the result so readers can see what the reported improvement means.
What the broader DFT claim does—and does not—establish
An IEEE presentation abstract describes AI-driven DFT solutions intended to optimize scan/ATPG pattern counts against coverage targets and reduce engineering effort and test cost. The abstract does not quantify those gains or identify a generally available product. It supports the existence of an industry-facing direction, not a vendor-specific capability claim or a measurable promise.
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A practical workflow for using AI in a test flow
- Name the objective. Decide whether the work is structural manufacturing test, functional workload testing, accelerator validation, burn-in stress, or another task. Record what a successful test is supposed to demonstrate. Do not use “test pattern” as if all of these objectives were interchangeable.
- Specify the design and fault context. For structural ATPG, identify the netlist, scan/DFT context, and targeted fault model. For functional generation, identify the accelerator or behavior under test and the rules a valid workload must satisfy. State whether the goal is fault detection, functional correctness, design coverage, or stress.
- Assign AI a bounded role. Choose a method that matches the objective: heuristic guidance for deterministic ATPG search, optimization of functional images, or LLM test generation with compiler and coverage feedback. Define what the AI proposes and what the existing tools must verify.
- Run the appropriate correctness check. For a structural pattern set, use fault simulation against the target fault list; the IEEE overview describes this as part of validating patterns before tape-out. For generated functional validation tests, check compiler acceptance and monitor design coverage as in the 2026 paper’s described flow. A plausible-looking vector is not evidence that it detects a fault or is a valid test.
- Inspect coverage and unresolved cases. Report the fault model, fault-list denominator, design or benchmark, and evaluation conditions. Distinguish an untestable fault from a search timeout or a fault that remains uncovered. A limited experiment or a failed search does not establish that every remaining fault is untestable.
- Measure the cost of using the patterns. Track pattern count and relevant generation cost, such as backtracks or CPU time, alongside the coverage objective. If compaction is used, verify that the required coverage is preserved. A reduction in search effort or vector count is useful only in relation to the test objective and deployment cost.
It can help to write down the acceptance criteria before comparing AI-assisted and conventional runs. For structural ATPG, that means naming the fault model and coverage target, then tracking search effort and pattern count. For functional validation, specify what counts as a correct test, which compiler or toolchain checks it, and how design coverage is measured. Defining these measures in advance makes it harder to confuse a faster search, a larger workload, or a higher design-coverage figure with success at a different task.
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How to evaluate a claimed AI-generated pattern result
When comparing methods, ask whether the result concerns structural scan ATPG or functional workloads; whether it depends on a netlist, scan data, compiler, or other toolchain; which faults or coverage target it addresses; and how generated artifacts were checked. Also ask which benchmark or device was tested, what metric improved, and whether the result is a research demonstration or a supported commercial product.
| Evaluation question | Why it matters |
|---|---|
| What is the objective: fault detection, functional correctness, design coverage, or stress? | These outcomes are not interchangeable, so a metric must match the actual job. |
| Which fault model and fault list were used? | Coverage applies to the modeled faults and cannot be interpreted without that context. |
| What design information and tools were inputs? | Netlist-based ATPG, scan-based flows, functional workloads, and compiler-checked tests have different dependencies. |
| How was correctness validated? | Fault simulation and compiler/design-coverage checks answer different questions. |
| What exactly improved, and against what baseline? | Backtracks, CPU time, pattern count, fault coverage, and design coverage measure different trade-offs. |
| Was the result demonstrated on benchmark circuits, one accelerator, or a production flow? | Evidence from one setting should not be generalized beyond the tested setting. |
| Is the method a research result or a supported product capability? | The cited papers and abstract do not establish a general drop-in commercial AI-ATPG offering. |
These comparison axes are useful because there is no single “AI pattern generation” score. Netlist dependence separates structural ATPG from methods designed to operate on functional behavior or workloads. The target metric separates fault coverage from design coverage and stress. Correctness checks, benchmarks, and integration dependencies show what a method actually required. Finally, a research prototype and a supported commercial offering are different kinds of evidence: conference results alone do not establish product availability or compatibility with a particular flow.
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- Order-of-magnitude fewer backtracks: reported by the authors of the 2022 IEEE paper for their benchmark-circuit PODEM implementation combining heuristics, compared with an implementation using any single heuristic. The paper also reports reduced CPU time; the result is not a universal runtime guarantee.
- 33% improvement in design coverage: reported in the abstract of the 2026 IEEE paper for its LLM-based hardware-accelerator validation framework and evaluation. It refers to design coverage in that setting, not a 33% increase in manufacturing fault coverage.
- High-volume coverage figures: the IEEE overview lists targets above 99% stuck-at coverage and above 95% transition-fault coverage on critical product lines. These are figures stated in that overview, not universal standards or appropriate targets for every design.
The coverage figures in the overview should be read as examples of targets it lists for critical product lines, not a requirement to apply to every chip or every project. Product, fault model, and use case determine the relevant objective. Similarly, the two research figures above measure different things: one reports search backtracks on benchmark circuits, while the other reports design coverage for functional accelerator validation. Neither can be substituted for a measured fault-coverage result in a target manufacturing flow.
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- Calling every generated vector ATPG. A generated functional workload is not structural ATPG unless it is tied to the relevant fault model and detection objective.
- Treating one coverage percentage as proof of quality. State the fault model or design-coverage definition, denominator, and evaluation setting.
- Assuming AI removes the need for scan or DFT. Scan architecture and testability are design-flow concerns; AI-assisted pattern search does not make them irrelevant.
- Equating compiler validity with fault detection. A compiler can check whether a functional test is acceptable to a toolchain; fault simulation checks detection against a modeled structural fault set.
- Generalizing a paper’s result to production. The cited numerical improvements are paper-specific results, not verified performance guarantees for other designs.
- Assuming fewer patterns always means a better test. Pattern reduction matters only if required coverage is preserved and the overall test-cost trade-off is acceptable.
What this evidence supports
The cited IEEE material supports several bounded uses of AI: guiding ATPG heuristics, optimizing functional patterns for particular accelerator targets, selecting functional stress patterns, and generating accelerator validation tests with feedback. It does not establish a general-purpose, commercially supported AI replacement for conventional structural ATPG. Treat AI as a component in a test flow, then validate the resulting artifacts with checks suited to the stated objective.
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For readers who want background on how ATPG connects to the tester, IEEE cites Cambridge’s Introduction to VLSI Design Flow as a technical resource on ATPG-to-ATE integration. Treat further reading as context for the design-to-tester flow, not as evidence that a specific AI product is available. Any vendor or product recommendation needs its own verification of current capabilities and support.
Frequently Asked Questions
Can AI generate ATPG patterns?
AI can guide a conventional deterministic ATPG search, as in the 2022 IEEE PODEM paper’s combined-heuristic approach. That is different from replacing the ATPG engine: patterns still need to meet a defined fault objective and be checked against the target fault list.
How do I validate AI-generated hardware test vectors?
Match the check to the task. For structural manufacturing patterns, run fault simulation against the specified fault model and fault list. For functional accelerator validation tests, check compiler acceptance and monitor design coverage. Compiler validity or design coverage alone does not prove manufacturing fault detection.
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Are functional accelerator tests the same as scan ATPG patterns?
No. Functional tests exercise workloads or behaviors, sometimes without scan shifting; structural scan ATPG uses design and scan context to seek patterns that detect modeled faults. A functional workload is not automatically a manufacturing test pattern.
Does a 33% design-coverage improvement mean 33% better fault coverage?
No. The 33% improvement is reported for the 2026 IEEE paper’s LLM-based accelerator validation framework and its design-coverage evaluation. Design coverage and manufacturing fault coverage are different measures.
What should I compare when evaluating an AI test-pattern method?
Compare the objective, netlist or scan dependencies, fault model or coverage definition, correctness checks, benchmark or device, and the metric improved. Also distinguish research results from supported commercial product capabilities.
The Bottom Line
AI can assist semiconductor test generation in bounded roles, from guiding ATPG heuristics to optimizing functional accelerator tests or generating validation tests with coverage feedback. Choose the approach by its objective, measure it with the corresponding coverage metric, and validate every artifact with checks suited to its intended use.
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